• VHDL Modeling: VHDL Test bench, Test benches using text files

The Test bench

use ieee.std_logic_1164.all;
entityhalf_adder_tb is

architecture TB_ARCHITECTURE of half_adder_tb is

-- Stimulus signals - signals mapped to the input

--and inout ports of tested entity

signal a : std_logic;
signal b : std_logic;

-- Observed signals - signals mapped to the output

--ports of tested entity

signal sum : std_logic;
signalcout : std_logic;

-- Design Under Test port map
DUT : entity work.half_adder(basic_struct)

port map (
a => a,
b => b,
sum => sum,
cout =>cout

-- your stimulus here ...

stimulus: process is
a <='0',
'1' AFTER 10 ns,
'0' AFTER 30 ns,
'1' AFTER 40 ns;
b <='0',
'0' AFTER 10 ns,
'1' AFTER 30 ns,
'1' AFTER 40 ns;
end process stimulus;

Read from File in VHDL using TextIO Library

When you need to simulate a design in VHDL it is very useful to have the possibility to read the stimuli to provide to your Design Under Test (DUT) reading from an input file.

This approach allows you to have different test bench input stimuli using the same VHDL test bench code.

In VHDL, there are predefined libraries that allow the user to read from an input ASCII file in a simple way. The TextIO library is the standard library that provides all the procedure to read from or write to a file. 

It is clear that these procedures cannot be used in a synthesizable RTL VHDL code, I mean no file handling possibility is present into a silicon device using simple RTL VHDL code, but they are very useful in test bench design.

There are several different ways to open a file and read from it.

In VHDL, File are handled as array of line. An example of VHDL syntax to read from file is:

-- Declare and Open file in read mode:
file file_handler : text open read_mode is “filename.dat”;
Variable row : line;
Variable v_data_read : integer;
-- in the concurrent or sequential section of the architecture
-- Read line from file
readline(file_handler, row);
-- Read value from line
read(row, v_data_read);

p_read : process(rstb,clk)


constant NUM_COL : integer := 2; -- number of column of file

type t_integer_array is array(integer range <> ) of integer;

file test_vector : text open read_mode is "file_name.txt";

variable row : line;
variable v_data_read : t_integer_array(1 to NUM_COL);
variable v_data_row_counter : integer := 0; if(rstb='0') then
v_data_row_counter := 0;
v_data_read := (others=> -1);
i_op1 <= (others=>'0');
i_op2 <= (others=>'0');


elsif(rising_edge(clk)) then
if(ena = '1') then -- external enable signal
-- read from input file in "row" variable
if(not endfile(test_vector)) then
v_data_row_counter := v_data_row_counter + 1;
end if;

-- read integer number from "row" variable in integer arra for kk in 1 to NUM_COL loop
end loop;

value1_std_logic_8_bit <= conv_std_logic_vector(v_data_read(1),8); value2_std_logic_8_bit <= conv_std_logic_vector(v_data_read(2),8);

end if;
end if;
end process p_read;


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Created by Vishal E on 2019/03/21 07:23
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