VLSI Design & Technology -BE E&TC- 2012 Course

Updated on 2019/07/24 06:33

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Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistorsinto a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

This cours explores the HDL and CMOS based design techniques, testability in logic circuit design, SoC issues and PLD architecture along with many interesting concepts in VLSI design.



VLSI Design & Technology


Final Year, Semester I



Examination Scheme

Phase I: In Semester Assessment30
Phase II: End Semester Examination70


Course Objectives

  • To study HDL based design approach.
  • To learn digital CMOS logic design.
  • To nurture students with CMOS analog circuit designs.
  • To realize importance of testability in logic circuit design.
  • To overview SoC issues and understand PLD architectures with advanced features.

Course Outcomes

After successfully completing the course, students will be able to:

  • Model digital circuit with HDL, simulate, synthesis and prototype in PLDs.
  • Understand chip level issues and need of testability.
  • Design analog & digital CMOS circuits for specified applications.

Syllabus and Notes

Unit I: VHDL Modeling

[Main Page: VHDL Modelling]

Unit II: PLD Architectures

[Main Page: PLD Architectures]

Unit III: SoC & Interconnect

[Main Page: SoC & Interconnect]

Unit IV: Digital CMOS Circuits

  • MOS Capacitor, MOS Transistor theory, C-V characteristics, Non ideal I-V effects, Technology Scaling.
  • CMOS inverters, DC transfer characteristics, Power components, Power delay product.
  • Transmission gate.
  • CMOS combo logic design.
  • Delays: RC delay model, Effective resistance, Gate and diffusion capacitance, Equivalent RC circuits; Linear delay model, Logical effort, Parasitic delay, Delay in a logic gate, Path logical efforts.

Unit V: Analog CMOS Design

  • Current sink and source, Current mirror.
  • Active load, Current source and Push-pull inverters.
  • Common source, Common drain, Common gate amplifiers.
  • Cascode amplifier, Differential amplifier, Operational amplifier.

Unit VI: Testability

  • Types of fault, Need of Design for Testability (DFT), Testability, Fault models, Path sensitizing, Sequential circuit test, BIST, Test pattern generation, JTAG & Boundary scan, TAP Controller.

Lab Practice

Main Page: VLSI Lab

List of Experiments:

  1. To write VHDL code, simulate with test bench, synthesis, implement on PLD. [Any 4].
    1. 4 bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR, & ALU pass.
    2. Universal shift register with mode selection input for SISO, SIPO, PISO, & PIPO modes.
    3. FIFO memory.
    4. LCD interface.
    5. Keypad interface.
  2. To prepare CMOS layout in selected technology, simulate with and without capacitive load, comment on rise, and fall times.
    1. Inverter, NAND, NOR gates, Half Adder
    2. 2:1 Multiplexer using logic gates and transmission gates.
    3. Single bit SRAM cell.
    4. D flip-flop.

Previous Years Questions

Practical/ Oral Exam Questions

  • Expected Questions


Assignment 1Assignment 2
Assignment 3Assignment 4
Assignment 5Assignment 6

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Created by Vishal E on 2019/03/21 07:23
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