## Port structure

### Ports of 8051

• There are four ports P0, P1, P2, and P3.
• Each port uses 8 pins.
• All I/O pins are bi-directional.
• The four I/O ports:
• Port 0 (Pins 32-39): P0（P0.0~P0.7）
• Port 1 (Pins 1-8): P1（P1.0~P1.7）
• Port 2 (Pins 21-28): P2（P2.0~P2.7）
• Port 3 (pins 10-17): P3（P3.0~P3.7)
• Each port has 8 pins.
• Named P0.X, P1.X, P2.X, P3.X; where (X=0,1,...,7)
• Ex: P0.0 is the bit 0 (LSB) of P0
• Ex: P0.7 is the bit 7 (MSB) of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction)

#### Port-0 Port-0 can be used as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory.

• When control is '1', the port is used for address/data interfacing.
• When the control is '0', the port can be used as a bidirectional I/O port.
##### Port-0 as Normal Input Port

Case I: Reading "High" on Pin P0.X  (Control Pin=0)

Internal CPU Bus (D Latch input)= 1
Output of D latch

•  which turns 'off' the lower FET while due to '0' control signal upper FET also turns off

Hence the output pin have floats hence "HIGH" data written on pin is directly read by read pin.

Case II: Reading "LOW" on Pin P0.X  (Control Pin=0)

Internal CPU Bus(D Latch input)= 1
Output of D latch

•  which turns 'ON' the lower FET while due to '0' control signal upper FET is turned off.

Hence the output pin have floats hence "LOW" data written on pin is directly read by read pin.

##### PORT-0 as Normal Output Port

Case I: Writing "High" on Pin P0.X  (Control Pin=0)

Internal CPU Bus(D Latch input)= 1
Output of D latch

•  which turns 'off' the lower FET while due to '0' control signal upper FET also turns off.

Here we want logic '1' on pin but we getting floating value so to convert that floating value into logic '1' we need to connect the pull up resistor parallel to upper FET. This is the reason why we needed to connect pull up resistor to port 0 when we want to initialize port 0 as an output port .

Case II: Writing "LOW" on Pin P0.X  (Control Pin=0)

Internal CPU Bus(D Latch input)= 0
Output of D latch

•  which turns 'ON' the lower FET while due to '0' control signal upper FET is turn off

The pin is pulled down by the lower FET. Hence the output becomes zero. ##### PORT-0 as Address or Data Bus

(When the control pin=1, address/data bus controls the output driver FETs.)

Case I: Writing "LOW" on Pin P0.X
If the address/data bus (internal) is '0',

• Upper FET = OFF.
• Lower FET =ON. The output becomes '0'.

Case II: Writing "High" on Pin P0.X
If the address/data bus (internal) is '0',

• Upper FET = ON. The output becomes '1'.
• Lower FET = OFF.

Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port-0 latch is written to with 1's when used for external memory access.

#### PORT-1

The structure of a port-1 pin is shown in fig below.It has 8 pins (P1.1-P1.7). ##### PORT-1 as Normal Input Port

Case I: Reading "High" on Pin P1.X

Internal CPU Bus(D Latch input)= 1
Output of D latch

•  which turns 'off' the FET

Hence the output pin have floats hence "HIGH" data written on pin is directly read by read pin.

Case II: Reading "LOW" on Pin P1.X

Internal CPU Bus(D Latch input)= 1
Output of D latch

•  which turns 'off' the FET.

Hence the output pins have floats and "LOW" data written on pin is directly read by read pin.

##### PORT-1 as Normal Output Port

Case I: Writing "High" on Pin P1.X

Internal CPU Bus(D Latch input)= 1
Output of D latch

•   which turns 'off' the lower FET

Hence at P1.X=VCC or logic '1' on pin .

Case II: Writing "LOW" on Pin P0.X  (Control Pin=0)

Internal CPU Bus(D Latch input)= 0
Output of D latch

•  which turns 'ON' the lower FET

The pin is pulled down by the lower FET.
Hence at P1.X = Ground or logic '0' on pin.
Hence the output becomes zero.

#### PORT-2

The structure of a port-2 pin is shown in fig. below. It has 8-pins (P2.0-P2.7) Port-2 we use for higher external address byte or a normal input/output port. The I/O operation is similar to Port-1.
Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability.

#### PORT-3

Port-3 (P3.0-P3.7) has alternate functions to each pin. The internal structure of a port-3 pin is shown in figure below. Alternate Functions of Port 3

• Bits P3.0 and P3.1 are used for the RxD (Receive Data) and TxD (Transmit Data) serial communications signals.
• Bits P3.2 and P3.3 are meant for external interrupts.
• Bits P3.4 and P3.5 are used for Timers 0 and 1.
• Bits P3.6 and P3.7 are used to provide the write and read signals of external memories connected in 8031 based systems

Sr. No.

Port 3 bit

Pin No

Function

1

P3.0

10

RxD

2

P3.1

11

TxD

3

P3.2

12

INT0

4

P3.3

13

INT1

5

P3.4

14

T0

6

P3.5

15

T1

7

P3.6

16

WR

8

P3.7

17

RD

#### References

• Created and edited by Prof. S.M.Wagh, SKNCOE, Pune
• WikiNote Foundation