Ethernet Protocol


The Ethernet protocol is made up of a number of components:

  1. Ethernet frames
  2. Physical Layer
  3. MAC operation

Ethernet Block of LPC1768



  • a full featured 10 Mbps or 100 Mbps Ethernet MAC (​Media Access Controller​)
  • optimized performance through the use of DMA hardware acceleration
  • a generous suite of control registers
  • half or full duplex operation
  • flow control
  • control frames
  • hardware acceleration for transmit retry
  • receive packet filtering
  • wake-up on LAN activity
  • Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU

Ethernet Block Architecture and Operation


The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix, it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum bandwidth to the Ethernet function.

The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced Media Independent Interface) protocol and the on-chip MIIM (Media Independent Interface Management) serial bus, also referred to as MDIO (Management Data Input/Output).

The block diagram of the Ethernet block - shown in the figure below - consists of:

  • The host registers module containing the registers in the software view and handling
  • AHB accesses to the Ethernet block. The host registers connect to the transmit and receive data path as well as the MAC.
  • The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access on-chip SRAM for reading of descriptors, writing of status, and reading and writing data buffers.
  • The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.
  • The transmit data path, including:
    • The transmit DMA manager which reads descriptors and data from memory and writes status to memory.
    • The transmit retry module handling Ethernet retry and abort situations.
    • The transmit flow control module which can insert Ethernet pause frames.
  • The receive data path, including:
    • The receive DMA manager which reads descriptors from memory and writes data and status to memory.
    • The Ethernet MAC which detects frame types by parsing part of the frame header.
    • The receive filter which can filter out certain Ethernet frames by applying different filtering schemes.
    • The receive buffer implementing a delay for receive frames to allow the filter to filter out certain frames before storing them to memory.

Block diagram


The block diagram of the Ethernet block

Ethernet packet fields


Ethernet packet fields

Frame Structure


Information is sent around an Ethernet network in discreet messages known as frames. The frame structure consists of the following fields:

Preamble: This consists of seven bytes, all of the form "10101010". This allows the receiver's clock to be synchronized with the sender's.

Start Frame Delimiter: ​This is a single byte ("10101011") which is used to indicate the start of a frame.

Destination Address: This is the address of the intended recipient of the frame. The addresses in 802.3 use globally unique hardwired 48 bit addresses.

Source Address: ​This is the address of the source, in the same form as above.

Length: This is the length of the data in the Ethernet frame, which can be anything from 0 to 1500 bytes.

Data: ​This is the information being sent by the frame.

Pad: 802.3 frame must be at least 64 bytes long, so if the data is shorter than 46 bytes, the pad field must compensate. The reason for the minimum length lies with the collision detection mechanism. In CSMA/CD the sender must wait at least two times the maximum propagation delay before it knows that no collision has occurred. If a station sends a very short message, then it might release the ether without knowing that the frame has been corrupted. 802.3 sets an upper limit on the propagation delay, and the minimum frame size is set at the amount of data which can be sent in twice this figure.

CRC: Cyclic Redundancy Check to detect errors that occur during transmission (DIX version of FCS).

FCS: Frame Check Sequence to detect errors that occur during transmission (802.3 version of CRC).


  • Prof. Sujit Wagh

Last modified: Wednesday, 16 October 2019, 5:30 AM