Internal RAM Oganization
This Internal RAM is found on-chip on the 8051 .So it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying it’s contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal RAM is organized as below.
- Four register banks (Bank0,Bank1, Bank2 and Bank3) each of 8-bits (total 32 bytes). The default bank register is Bank0. The remaining Banks are selected with the help of RS0 and RS1 bits of PSW Register.
- 16 bytes of bit addressable area and
- 80 bytes of general purpose area (Scratch pad memory) as shown in the diagram below. This area is also utilized by the microcontroller as a storage area for the operating stack.
The 32 bytes of RAM from address 00 H to 1FH are used as working registers organized as four banks of eight registers each.The registers are named as R0-R7 .Each register can be addressed by its name or by its RAM address.
For EX : MOV A, R7 or MOV R7,#05H
Register bank to be selected using RS1,RS0 bits from Program status word register
|RS1||RS0||Register Bank||RAM Address|
|0||0||Register Bank 0 (Slected as by default)||00H-07H|
|0||1||Register Bank 1 (Stack memory)||08H-0FH|
|1||0||Register Bank 2||10H-17H|
|1||1||Register Bank 3||18H-1FH|
- Internal ROM occupies the code address space from 0000H to 0FFFH (Size = 4K byte)
- Program addresses higher than 0FFFH will automatically fetch code bytes from external program memory
- Code bytes can also be fetched exclusively from an external memory by connecting the external access pin (EA) to ground
External program memory interfacing with 8051
- EA pin is active low input pin so if EA=0 or connected to ground the code bytes will be fetched from External Program memory
- ALE(Address Latch Enable)= indicates the Adress Latch is enabled
External Data memory interfacing with 8051
- EA pin is active low input pin so if EA=1 the code bytes will be fetched from External Data memory
- ALE(Address Latch Enable)=1 indicates the Adress Latch is enabled
- Created and designed by Prof S.M.Wagh, Sinhgad's SKNCOE, Pune