Pipeline Operation in TMS320C67X
Pipeline Operation Overview
The pipeline phases are divided into three stages:
All instructions in the C67x DSP instruction set flow through the fetch, decode,and execute stages of the pipeline.
The fetch stage of the pipeline has four phases for all instructions,
and the decode stage has two phases for all instructions.
The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction.
The stages of the C67x DSP pipeline are shown in Figure.
The fetch phases of the pipeline are:
- PG: Program address generate
- PS: Program address send
- PW: Program access ready wait
- PR: Program fetch packet receive
The C67x DSP uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch processing together, through the PG, PS,PW, and PR phases.
Figure 4−2(a) shows the fetch phases in sequential order from left to right.
Figure 4−2(b) is a functional diagram of the flow of instructions through the fetch phases.
During the PG phase, the program address is generated in the CPU.
In the PS phase, the program address is sent to memory.
In the PW phase, a memory read occurs.
Finally, in the PR phase, the fetch packet is received at the CPU.
Figure 4−2(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline.
In Figure 4−2(c), the first fetch packet (in PR) is made up of four execute packets, and the second and third fetch packets (in PW and PS) contain two execute packets each.
The last fetch packet (in PG) contains a single execute packet of eight single-cycle instructions.
The decode phases of the pipeline are:
- DP: Instruction dispatch
- DC: Instruction decode.
In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute packets consist of one instruction or from two to eight parallel instructions. During the DP phase, the instructions in an execute packet are assigned to the appropriate functional units.
In the DC phase, the the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units.
Figure shows the decode phases in sequential order from left to right.
Figure,shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instructions of the fetch packet (FP) are parallel and form an execute packet (EP).
This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each instruction’s assigned functional unit for execution during the same cycle.The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it.The first two slots of the fetch packet (shaded below) represent an execute packet of two parallel instructions that were dispatched on the previous cycle.This execute packet contains two MPY instructions that are now in decode(DC) one cycle before execution. There are no instructions decoded for the .L,.S, and .D functional units for the situation illustrated.
The execute portion of the pipeline is subdivided into ten phases (E1−E10),as compared to the five phases in a fixed-point pipeline. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important role in your understanding the device state at CPU cycle boundaries. The execution of different types of instructions in the pipeline is described in section 4.2, Pipeline Execution of Instruction Types. Figure 4−4(a) shows the execute phases of the pipeline in sequential order from left to right. Figure 4−4(b) shows the portion of the functional block diagram in which execution occurs.
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