Parallel Operations in TMS320C67XX DSP Processor

Parallel Operations in TMS320C67XX DSP Processor


Instructions are always fetched eight at a time. This constitutes a fetch packet.The basic format of a fetch packet is shown in Figure. Fetch packets are aligned on 256-bit (8-word) boundaries.

fetch-packet-basic-format.jpg

The execution of the individual instructions is partially controlled by a bit in each instruction, the p-bit. The p-bit (bit 0) determines whether the instruction executes in parallel with another instruction. The p-bits are scanned from left to right (lower to higher address). If the p-bit of instruction i is 1, then instruction i + 1 is to be executed in parallel with (in the the same cycle as) instruction i.If the p-bit of instruction i is 0, then instruction i + 1 is executed in the cycle after instruction i. All instructions executing in parallel constitute an execute packet.An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit.On the C67x DSP, an execute packet cannot cross an 8-word boundary;therefore, the last p-bit in a fetch packet is always cleared to 0, and each fetch packet starts a new execute packet. On the C67x+ DSP, an execute packet can cross an 8-word boundary.There are three types of p-bit patterns for fetch packets.

These three p-bit patterns result in the following execution sequences for the eight instructions:

  • Fully serial
  • Fully parallel
  • Partially serial

Example show the conversion of a p-bit sequence into a cycle-by-cycle execution stream of instructions.

1) Fully Serial


FULLY_SERIAL

This P-bit pattern results in this execution of sequence;-The all eight instructions are executed sequentially

 Clock Cycle / Packet Execution Instructions
 1 A
 2 B
 3 C
 4 D
 5 E
 6 F
 7 G
 8 H

2) Fully Parallel


FULLY_PARALLEL

This P-bit pattern results in this execution of sequence :- The all eight instructions are executed parallely.

Clock Cycle / Packet Execution Instructions
 1 A, B,C,D,E,F,G,H

3) Partially Serial


PARTIALLY_SERIAL

This P-bit pattern results in this execution of sequence :- The all eight instructions are executed parallely.

 Clock Cycle / Packet Execution Instructions
 1 A
 2 B
 3 C,D,E
 4 F,G,H

Example Parallel Code

The vertical bars || signify that an instruction is to execute in parallel with theprevious instruction. The code for the fetch packet in Example 3−3 would be represented as this:

                                        instruction A
                                        instruction B
                                        instruction C
                                      || instruction D
                                      || instruction E
                                        instruction F
                                     || instruction G
                                     || instruction H

References



  • WikiNote Foundation

Last modified: Sunday, 3 May 2020, 6:30 PM