Conditional Operations in TMS320C67X DSP Procesoor
Most instructions can be conditional. The condition is controlled by a 3-bit opcode field (creg) that specifies the condition register tested, and a 1-bit field(z) that specifies a test for zero or nonzero. The four MSBs of every opcode are creg and z. The specified condition register is tested at the beginning of the E1 pipeline stage for all instructions. If z = 1, the test is for equality with zero; if z = 0, the test is for nonzero. The case of creg = 0 and z = 0 is treated as always true to allow instructions to be executed unconditionally. The creg field is encoded in the instruction opcode as shown in Table
Conditional instructions are represented in code by using square brackets, [ ],surrounding the condition register name. The following execute packet contains two ADD instructions in parallel. The first ADD is conditional on B0 being nonzero. The second ADD is conditional on B0 being zero. The character! indicates the inverse of the condition.
[B0] ADD .L1 A1,A2,A3 // Perform A3= A2+A1 using .L1 unit only if value in B0 register is Non-Zero i.e. Z flag bit=0
|| [!B0] ADD .L2 B1,B2,B3 // Perform B3= B1+B2 using .L2 unit only if value in B0 register is Zero i.e. Z flag bit=1
The above instructions are mutually exclusive, only one will execute. If they are scheduled in parallel, mutually exclusive instructions are constrained. If mutually exclusive instructions share any resources, they cannot be scheduled in parallel (put in the same execute packet), even though only one will execute.
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