Addressing Modes in TMS320C67XX

Addressing Modes


Addresssing Mode  Syntax Registers Used Functional Unit Used Mnemonic Used
Register Addressing mode mnemonic .unit scr1, scr2, dst All 32 Registers
A0-A15 , B0-B15
 .L1, .L2, .M1, .M2, .S1,.S2,.D1,.D2
Any one can be used depending upon instruction
 ADD, SUB, MPY 
 Linear Addressing mode mnemonic .unit mode field, dst All 32 Registers
A0-A15 , B0-B15
 Uses .D1 and .D2 Load, Store
Circular Addressing mode mnemonic .unit mode field, dstA4-A7
B4-B7
 .D1 unit of Register Path A
 .D2 unit of Register Path B
 Load, Store

Register Addressing mode


 mnemonic .unit scr1, scr2, dst

Example:-

Instruction  Description Functional Unit used
 ADD .L1 A1, A2, A3 A3= A1+ A2 .L1
 ADD .S2 B1, B2 B2= B1+B2 .S2
 ADD .L1X  A1, B2, A2 A2= A1+ B2   X- Cross Path .L1

Linear Addressing mode


mnemonic .unit mode field, dst

Example :-

Instruction  Description
 LDW .D1 *A0[1], A1Load hexadecimal word from memory to register A1. The address of the memory is the base address value in register A0 added with 5-bit constant offset given in bracket left shifted by 2 bit position. (left shift by 3, 2, 1, 0 for double word, word, half word, byte respt.)
 LDW .D1 *++A0[A4], A1Load hexadecimal word from memory to register A1. The address of the memory is the base address value in register A0 added with contents of Register A4 offset given in bracket left shifted by 2 bit position.(Left shift by 3, 2, 1, 0 for double word, word, half word, byte respt.)

LDW .D1 *A0++[2], A1

Load hexadecimal word from memory to register A1. The address of the memory is the base address value in register A0 .After  accessing the memory the new address in A0 is  contents of A0 added with 5-bit constant offset given in bracket left shifted by 2 bit position(Left shift by 3, 2, 1, 0 for double word, word, half word, byte respt.)

*+baseR[offsetR/ucst5]   Positive offset from baseR specified by offserR/ucst5

*-baseR[offsetR/ucst5 ] Negative offset from baseR specified by offserR/ucst5

*++baseR[offsetR/ucst5]   Pre-incrmt from baseR specified by offserR/ucst5

*--baseR[offsetR/ucst5 ]  Pre-decrmt from baseR specified by offserR/ucst5

*baseR++[offsetR/ucst5 ]  Post-incrmt from baseR specified by offserR/ucst5

*baseR--[offsetR/ucst5  Post-decrmt from baseR specified by offserR/ucst5

The addressing modes on the C67x DSP are linear, circular using BK0, and circular using BK1. The addressing mode is specified by the addressing mode register (AMR)..All registers can perform linear addressing. Only eight registers can perform circular addressing: A4−A7 are used by the .D1 unit and B4−B7 are used by the .D2 unit. No other units can perform circular addressing.LDB(U)/LDH(U)/LDW, STB/STH/STW, ADDAB/ADDAH/ADDAW/ADDAD,and SUBAB/SUBAH/SUBAW instructions all use AMR to determine what type of address calculations are performed for these registers.

Circular Addressing mode


  • Uses .D1 and .D2
  • A4-A7 and B4-B7 are used
  • Address mode register is used to select modes for A4/B4—A7/B7
  • mnemonic .unit mode field, dst

image-20190506211916-1.jpg

References


  • WikiNote Foundation

Last modified: Friday, 20 September 2019, 3:20 PM