Interrupts-in-TMS320C67XX DSP Processor

Interrupts in TMS320C6XX DSP Processor

Typically, DSPs work in an environment that contains multiple external asynchronous events. These events require tasks to be performed by the DSP when they occur. An interrupt is an event that stops the current process in the CPU so that the CPU can attend to the task needing completion because of the event. These interrupt sources can be on chip or off chip, such as timers, analog-to-digital converters, or other peripherals. Servicing an interrupt involves saving the context of the current process, completing the interrupt task, restoring the registers and the process context, and resuming the original process. There are eight registers that control servicing interrupts.
An appropriate transition on an interrupt pin sets the pending status of the interrupt within the interrupt flag register (IFR). If the interrupt is properly enabled, the CPU begins processing the interrupt and redirecting program flow to the interrupt service routine.

Types of Interrupts and Signals Used

There are three types of interrupts on the CPUs of the TMS320C6000DSPs.

  • Reset
  • Maskable
  • Nonmaskable

These three types are differentiated by their priorities, as shown in Table

The reset interrupt has the highest priority and corresponds to the RESET signal.
The nonmaskable interrupt has the second highest priority and corresponds to the NMI signal.
The lowest priority interrupts are interrupts 4−15 corresponding to the INT4−INT15 signals. RESET, NMI, and some of the INT4−INT15 signals are mapped to pins on C6000 devices. Some of the INT4−INT15 interrupt signals are used by internal peripherals and some may be unavailable or can be used under software control. Check your device specific data manual to see your interrupt specifications.

Reset (RESET)

Reset is the highest priority interrupt and is used to halt the CPU and return it to a known state. The reset interrupt is unique in a number of ways:

  • RESET is an active-low signal. All other interrupts are active-high signals.
  • RESET must be held low for 10 clock cycles before it goes high again toreinitialize the CPU properly.
  • The instruction execution in progress is aborted and all registers are returned to their default states.
  • The reset interrupt service fetch packet must be located at address 0.
  • RESET is not affected by branches.
Nonmaskable Interrupt (NMI)

NMI is the second-highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as imminent power failure.
For NMI processing to occur, the nonmaskable interrupt enable (NMIE) bit in the interrupt enable register must be set to 1. If NMIE is set to 1, the only condition that can prevent NMI processing is if the NMI occurs during the delay slots of a branch (whether the branch is taken or not).
NMIE is cleared to 0 at reset to prevent interruption of the reset. It is cleared at the occurrence of an NMI to prevent another NMI from being processed.
You cannot manually clear NMIE, but you can set NMIE to allow nested NMIs. While NMI is cleared, all maskable interrupts (INT4−INT15) are disabled.

Maskable Interrupts (INT4−INT15)

The CPUs of the C6000 DSPs have 12 interrupts that are maskable. These have lower priority than the NMI and reset interrupts. These interrupts can be associated with external devices, on-chip peripherals, software control, or not be available.
Assuming that a maskable interrupt does not occur during the delay slots of a branch (this includes conditional branches that do not complete execution
due to a false condition), the following conditions must be met to process a maskable interrupt:

  • The global interrupt enable bit (GIE) bit in the control status register (CSR) is set to1.
  • The NMIE bit in the interrupt enable register (IER) is set to1.
  • The corresponding interrupt enable (IE) bit in the IER is set to1.
  • The corresponding interrupt occurs, which sets the corresponding bit in the interrupt flags register (IFR) to 1 and there are no higher priority interrupt flag (IF) bits set in the IFR.

Interrupt Acknowledgment (IACK) and Interrupt Number (INUMn)

The IACK and INUMn signals alert hardware external to the C6000 that an interrupt has occurred and is being processed. The IACK signal indicates that the CPU has begun processing an interrupt. The INUMn signal (INUM3−INUM0) indicates the number of the interrupt (bit position in the IFR) that is being processed. For example:
INUM3 = 0 (MSB)
INUM2 = 1
INUM1 = 1
INUM0 = 1 (LSB)
Together, these signals provide the 4-bit value 0111, indicating INT7 is being processed.


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Last modified: Friday, 20 September 2019, 3:16 PM