On-chip Peripherals of TMS320C67XX DSP Processor
On-chip Peripherals of TMS320C6XX DSP Processor
Question- Enlist the On – Chip peripherals of TMS320C67X processor and explain any two in details
Answer- On-chip periphrals are
- Multichannel Buffered Serial Port0 (McBSP0)
- Multichannel Buffered Serial Port1 (McBSP1)
- Interrupt Selector
Explanation of McBSP
- Provides full-duplex communication
- Data selection size of 8,12,16,20,24 and 32 bits
- Independent framing and clocking for receive and transmit
- External shift clock or internal programmable clock for data for transfer
- 8-bit data transfer with an option of LSB or MSB first
- Programmable polarity for both frame synchronization and data clocks
- Double buffered register which allows continuous data transmission
- Auto buffering capability through 5- channel DMA controller
- µ law and A law companding
- Direct interface to industry standard codecs, A/D, D/A converters etc.
The C6000™ DSP device has 32-bit general-purpose timers that can be used to:
- Time events
- Count events
- Generate pulses
- Interrupt the CPU
- Send synchronization events to the DMA
The timers have two signaling modes and can be clocked by an internal or an external source. The timers have an input pin and an output pin. The input and output pins (TINP and TOUT) can function as timer clock input and clock output. They can also be respectively configured for general-purpose input and output. With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count external events and interrupt the CPU after a specified number of events. Table 1 summarizes the differences between the C6000 timers. Figure 1 shows a block diagram of the timers.
Configuring a timer requires four basic steps:
1. If the timer is not currently in the hold state, place the timer in hold (HLD = 0). Note that after device reset, the timer is already in the hold state.
2. Write the desired value to the timer period register (PRD).
3. Write the desired value to the timer control register (CTL). Do not change the GO and HLD bits in CTL.
4. Start the timer by setting the GO and HLD bits in CTL to 1.
Table 2 describes how using the GO and HLD bits in the timer control register (CTL) enable basic features of timer operation.
|Holding the timer||0||0||Counting is disabled.|
|Restarting the timer after hold||0||1||Timer continues from the value before hold. The timer counter is not reset.|
|Starting the timer||1||1||Timer counter resets to 0 and starts counting whenever enabled. Once set, GO self-clears.|
The timer counter runs at the CPU clock rate. However, counting is enabled on the low-to-high transition of the timer count enable source. This transition is detected by the edge-detect circuit shown in Figure 1. Each time an active transition is detected, one CPU-clock-wide clock enable pulse is generated. This makes the counter appear as if it were getting clocked by the count enable source. Thus, this count enable source is referred to as the timer input clock source. Once the timer reaches a value equal to the value in the timer period register (PRD), the timer is reset to 0 on the next CPU clock. Thus, the counter counts from 0 to N.
Timer Clock Source Selection
Low-to-high transitions (or high-to-low transitions, if INVINP = 1) of the timer input clock allow the timer counter to increment. Two sources are available to drive the timer input clock: • The input value on the TINP pin, selected by CLKSRC = 0. This signal is synchronized to prevent any metastability caused by asynchronous external inputs. The value present on the TINP pin is reflected by DATIN. • Internal clock source, selected by CLKSRC = 1. The C62x/C67x DSPs use CPU clock/4 as an internal clock source. The C64x DSPs use CPU clock/8 as an internal clock source.
Timer Pulse Generation
The two basic pulse generation modes are pulse mode ( Figure 2) and clock mode ( Figure 3). You can select the mode with the CP bit in the timer control register (CTL). Note that in pulse mode, PWID in the CTL can set the pulse width to either one or two input clock periods. The purpose of this feature is to provide minimum pulse widths if TSTAT drives the TOUT output. TSTAT drives this pin when TOUT is used as a timer pin (FUNC = 1), and may be inverted by setting INVOUT = 1. Table 3 gives equations for various TSTAT timing parameters in pulse and clock modes.
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