External-Memory-Interface

External Memory Interface


The C6457 DSP EMIF interfaces to a variety of external devices, including:

  • Pipelined and flow-through synchronous-burst SRAM (SBSRAM)
  • ZBT (zero bus turnaround) SRAM and Late Write SRAM
  • Synchronous FIFOs
  • Asynchronous memory, including SRAM, ROM, and Flash

A block diagram of the C6457 DSP is shown in Figure 1. In this document, the term EMIF refers to the EMIFA of C6457 devices.

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The EMIF services requests of the external bus from on-chip masters such as the enhanced direct-memory access (EDMA) controller and the C64x+ Megamodule, as well as external shared-memory device controllers (through the hold interface, Section 10). On-chip masters place requests to the EMIF through the switched control resource (SCR). With a 32-bit address bus, the total memory space is 2^32= 4GB, including four external memory spaces: CE0, CE1, CE2, and CE3.

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EMIF Interface Signals


The EMIF signals of the DSP are shown in the figure below and described in the following tables. The EMIF has the following features:

  • A 64-bit data bus which can also be configured to be 32-, 16-, and 8-bits wide.
  • An output clock, ECLKOUT, generated internally based on the EMIF input clock. You can select one of the following two clocks as the EMIF input clock source at device reset: internal SYSCLK7 or external ECLKIN. All of the memories interfacing with the EMIF should operate using ECLKOUT (EMIF clock cycle). The ECLKOUT frequency equals the EMIF input clock frequency.
  • A programmable synchronous interface allowing glueless interfaces to synchronous devices such as ZBT SRAM, Late Write SRAM, and Pipelined and Flow-Through SBSRAM devices. Interfaces to synchronous FIFOs are also supported with the addition of external logic.
  • A configurable asynchronous interface allowing interfaces to asynchronous devices such as SRAM, EPROM, and Flash, as well as FPGA and ASIC designs.
  • Four EMIF spaces (CE2-5) reserved for either asynchronous or synchronous memory accesses. 

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Last modified: Friday, 20 September 2019, 3:01 PM