Internal Memory of TMS320C67XX DSP Processor

Internal Memory of TMS320C6xx DSP processor

TMS320C621x/C671x Two-Level Internal Memory

The TMS320C621x, TMS320C671x, and TMS320C64x digital signal processors (DSPs) of the TMS320C6000  DSP family have a two-level memory architecture for program and data. The first-level program cache is designated L1P, and the first-level data cache is designated L1D. Both the program and data memory share the second-level memory, designated L2. L2 is configurable, allowing for various amounts of cache and SRAM. This section discusses the C621x/C671x two-level internal memory.

Memory Hierarchy Overview


Access level of Memory Map

L1 Memory

  • Cache-based Architecture
  • Program Cache (PC) & Data Cache (DC)
  • Size : PC(4Kbyte), DC(4Kbyte)

L2 Memory

  • Size : 64Kbyte
  • Program & Data

L3 Memory

  • External Memory

Internal MemoryThe C67x DSP has a 32-bit, byte-addressable address space. Internal(on-chip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF).The C67x DSP has two 32-bit internal ports to access internal data memory.The C67x DSP has a single internal port to access internal program memory,with an instruction-fetch width of 256 bits.



  1. Independent memory banks on the C6x allow for two memory accesses within one instruction cycle.
  2. Two independent memory banks can be accessed using two independent buses.
  3. Two loads or two stores instructions can be performed in parallel.
  4. No conflict results if the data accessed are in different memory banks.
  5. Separate buses for program, data, and direct memory access (DMA) allow the C6x to perform concurrent program fetches, data read and write, and DMA operations.
  6. C6x has a byte-addressable memory space.
  7. Internal memory is organized as separate program and data memory spaces, with two 32- bit internal ports (two 64-bit ports with the C64x) to access internal memory.
  8. With a clock of 150MHz onboard the DSK, one can ideally achieve two multiplies and accumulates per cycle, for a total of 300 million multiplies and accumulates (MACs) per second.



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Last modified: Friday, 20 September 2019, 2:53 PM