TMS320C67X CPU Data Path and Control

CPU Data Paths


The components of the data path for the TMS320C67x CPU are shown in Figure below. These components consist of:

  • Two general-purpose register files (A and B) 
  • Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2) 
  • Two load-from-memory data paths (LD1 and LD2) 
  • Two store-to-memory data paths (ST1 and ST2) 
  • Two data address paths (DA1 and DA2) 
  • Two register file data cross paths (1X and 2X)


General-Purpose Register Files

There are two general-purpose register files (A and B) in the C6000 data paths.For the C67xDSP, each of these files contains 16 32-bit registers (A0–A15 for file A and B0–B15 for file B), as shown in Table below. For the C67x+ DSP, theregister file size is doubled to 32 32-bit registers (A0–A31 for file A and B0–B21for file B), as shown in Table below. The general-purpose registers can be usedfor data, data address pointers, or condition registers.

The C67x DSP general-purpose register files support data ranging in size frompacked 16-bit data through 40-bit fixed-point and 64-bit floating point data.Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, arestored in register pairs. In these the 32 LSBs of data are placed in an evennumberedregister and the remaining 8 or 32 MSBs in the next upper register(that is always an odd-numbered register). Packed data types store either four8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit valuesin a 64-bit register pair.

There are 16 valid register pairs for 40-bit and 64-bit data in the C67x DSPcores. In assembly language syntax, a colon between the register namesdenotes the register pairs, and the odd-numbered register is specified first.

The additional registers are addressed by using the previously unused fifth(msb) bit of the source and register specifiers. All 64-bit register writes andreads are performed over 2 cycles as per the current C67x devices.

Figure 2−2 shows the register storage scheme for 40-bit long data. Operationsrequiring a long input ignore the 24 MSBs of the odd-numbered register.Operations producing a long result zero-fill the 24 MSBs of the odd-numberedregister. The even-numbered register is encoded in the opcode.

40 bit/ 64 bit Register Pairs
Register Files  Register Files
 A B
 A1:A0 B1:B0
 A3:A2 B3:B2
 A5:A4 B5:B4
 A7:A6 B7:B6
 A9:A8 B9:B8
 A11:A10 B11:B10
 A13:A12 B13:B12
 A15:A14 B15:B14
Storage Scheme for 40-bit Data in a Register Pair


Functional Unit

The eight functional units in the C6000 data paths can be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. The functional units are described in Table below.Most data lines in the CPU support 32-bit operands, and some support long(40-bit) and double word (64-bit) operands. Each functional unit has its own 32-bit write port into a general-purpose register file (Refer to Figure 2−1). All units ending in 1 (for example, .L1) write to register file A, and all units ending in 2 write to register file B. Each functional unit has two 32-bit read ports for source operands src1 and src2. Four units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as well as an 8-bit input for 40-bit long reads. Because each unit has its own 32-bit write port, when performing 32-bit operations all eight units can be used in parallel every cycle.

Functional Units and Operations Performed
Name of the Functional Unit.L unit.S unit.M unit.D unit
Type of operation    
Arithmetic operation32/40 bit operation32 bit operation-32 bit add and subtract operations only
Logical operation32-bit operations32-bit operations-32-bit logical operations*
Multiply operations--16x16 multiply operations-
Shift operations-32/40 bit shift operations--
Compare operations32/40 bit operation---
Branch operations-Yes--
Load and Store operations---Loads and stores with 5-bit constant offset(15 bit constant offset in .D2 only)
Linear and circular address calculation---Yes
Constant generation-Yes--
Count operations32/40 bit count operations---
Move operationsRegister to register only16 bit move operations-Register to register only

Register File Cross Paths

Each functional unit reads directly from and writes directly to the register file within its own data path. That is, the .L1, .S1, .D1, and .M1 units write to register file A and the .L2, .S2, .D2, and .M2 units write to register file B. The register files are connected to the opposite-side register file’s functional units via the 1X and 2X cross paths. These cross paths allow functional units from one data path to access a 32-bit operand from the opposite side register file. The 1X cross path allows the functional units of data path A to read their source from register file B, and the 2X cross path allows the functional units of data path B to read their source from register file A.On the C67x DSP, six of the eight functional units have access to the register file on the opposite side, via a cross path. The .M1, .M2, .S1, and .S2 units’ src2 units are selectable between the cross path and the same side register file. In the case of the .L1 and .L2, both src1 and src2 inputs are also selectable between the cross path and the same-side register file.Only two cross paths, 1X and 2X, exist in the C6000 architecture. Thus, the limit is one source read from each data path’s opposite register file per cycle,or a total of two cross path source reads per cycle. In the C67x DSP, only one functional unit per data path, per execute packet, can get an operand from the opposite register file.

Memory, Load, and Store Paths

The C67x DSP has two 32-bit paths for loading data from memory to the register file: LD1 for register file A, and LD2 for register file B. The C67x DSP also has a second 32-bit load path for both register files A and B. This allows the LDDW instruction to simultaneously load two 32-bit values into register file A and two 32-bit values into register file B. For side A, LD1a is the load path for the 32 LSBs and LD1b is the load path for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs and LD2b is the load path for the 32 MSBs. There are also two 32-bit paths, ST1 and ST2, for storing register values to memory from each register file.

Data Address Path

The data address paths (DA1 and DA2) are each connected to the .D units in both data paths. This allows data addresses generated by any one path to access data to or from any register.The DA1 and DA2 resources and their associated data paths are specified as T1 and T2, respectively. T1 consists of the DA1 address path and the LD1 andST1 data paths. For the C67x DSP, LD1 is comprised of LD1a and LD1b tosupport 64-bit loads. Similarly, T2 consists of the DA2 address path and the LD2 and ST2 data paths. For the C67x DSP, LD2 is comprised of LD2a and LD2b to support 64-bit loads.The T1 and T2 designations appear in the functional unit fields for load and store instructions. For example, the following load instruction uses the .D1 unit to generate the address but is using the LD2 path resource from DA2 to place the data in the B register file. The use of the DA2 resource is indicated with the T2 designation. 
 LDW .D1 T2 *A0[3], B1

Control Registers

Register NameAcronymDescription
Addressing Mode Reg.AMRSpecifies linear or circular addressing of A4-A7 &B4-B7
Control Status Reg.CSRContains important control and status bits of the processor
Program Counter  E1 Phase Reg.PCE1Contains the address of the fetch packet that is in the E1 phase of the pipeline
Interrupt Flag Reg.IFRContains the status of INT4-INT5 and NMI maskable interrupts
Interrupt Set Reg.ISRUsed to manually set maskable pending interrupts
Interrupt Clear Reg.ICRUsed to manually clear maskable pending interrupts
Interrupt Enable Reg.IERUsed to enable/disable the individual maskable interrupts
Interrupt Service Table Reg.ISTPPoints to beginning of interrupt service table
Interrupt Return PointerIRPContains the address to be used to return from a maskable interrupt
Non-maskable Interrupt Return PointerNRPContains the address to be used to return from a non-maskable interrupt

Addressing Mode Register (AMR)

With circular addressing, the field also specifies which BK (block size) field to use for a circular buffer. In addition, the buffer must be aligned on a byte boundary equal to the block size. The mode select fields and block size fields are shown in Figure below and described in Table
For each of the eight registers (A4–A7, B4–B7) that can perform linear or circular addressing, the addressing mode register (AMR) specifies the addressing mode. A 2-bit field for each register selects the address modification mode : linear (the default) or circular mode.

Structure of AMR
 Symbol Reserved BK1 Field BK0 Field
B7 Mode
select bits 
 B6 Mode
select bits
 B5 Mode
select bits
 B4 Mode
select bits
 A7 Mode
select bits
 A6 Mode
select bits
 A5 Mode
select bits
 A4 Mode
select bits
 Bits 31-26 25-21 20-16 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0
Mode SelectDescription of mode
00Linear modification of address
01Circular addressing using BK0 field
10Circular addressing using BK1 field

Control Status Register

Structure of CSR
 Symbol CPU_ID Revision ID PWRD
 Bits 31-24 23-16 15-10 9 8 7-6-54-3-2 1 0

Bits 0 to 7 and 10 to 15 are Readable & Writeable
Bits 8, 9 and 16 to 23 are only Readable

CPU_ID Field (8-bits)Family of DSP Processor
00HC62X Family of DSP Processor
01HC67X Family of DSP Processor
02HC64X Family of DSP Processor

Revision ID - Silicon Version of CPU
PWRD bits - Power Down Mode Bits - Values always read as '0'
SAT- Saturation bit =1 ; Indicates Functional Unit has executed saturate instructions
EN (ENDIAN) - 1 = Little Endian (Data Storing method in memory)
                     - 0 = Big Endian
PCC - Program Cache Control Mode
DCC - Data Cache Control Mode
PGIE - Previous Global Interrupt Enable Bit
GIE - 1 ; Enable all Maskable Interrupts
       - 0 ; Disable


  • TMS320C67X Datasheet
  • Created and Edited by Prof Sujit Wagh, Sinhgad's SKNCOE, Pune
  • WikiNote Foundation

Last modified: Friday, 20 September 2019, 2:44 PM