Architecture of TMS320C67X DSP Processor
Architecture of TMS320C67X DSP Processor
Figure below is the block diagram for the C67x DSP. The C6000 devices comewith program memory, which, on some devices, can be used as a programcache. The devices also have varying sizes of data memory. Peripherals suchas a direct memory access (DMA) controller, power-down logic, and externalmemory interface (EMIF) usually come with the CPU, while peripherals suchas serial ports and host ports are on only certain devices. Check the data sheetfor your device to determine the specific peripheral configurations you have.
Central Processing Unit (CPU)The C67x CPU,
in Figure above, is common to all the C62x/C64x/C67x devices.
The CPU contains:
- Program fetch unit
- Instruction dispatch unit
- Instruction decode unit
- Two data paths, each with four functional units
- 32 32-bit registers
- Control registers
- Control logic Test, emulation, and interrupt logic
The program fetch, instruction dispatch, and instruction decode units candeliver up to eight 32-bit instructions to the functional units every CPU clockcycle. The processing of instructions occurs in each of the two data paths (Aand B), each of which contains four functional units (.L, .S, .M, and .D) and 1632-bit general-purpose registers. The data paths are described in more detailin Chapter 2. A control register file provides the means to configure and controlvarious processor operations. To understand how instructions are fetched,dispatched, decoded, and executed in the data path will see later.
- Internal MemoryThe C67x DSP has a 32-bit, byte-addressable address space.
- Internal(on-chip) memory is organized in separate data and program spaces.
- When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF).
- The C67x DSP has two 32-bit internal ports to access internal data memory.
- The C67x DSP has a single internal port to access internal program memory,with an instruction-fetch width of 256 bits.
Features of C67X DSP Processor
Features of the C6000 devices include:
- Advanced VLIW CPU with eight functional units, including two multipliersand six arithmetic units
- Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
- Allows designers to develop highly effective RISC-like code for fast development time
- Instruction packing
- Gives code size equivalence for eight instructions executed serially or in parallel
- Reduces code size, program fetches, and power consumption
- Conditional execution of all instructions
- Reduces costly branching
- Increases parallelism for higher sustained performance
- Efficient code execution on independent functional units
- Industry’s most efficient C compiler on DSP benchmark suite
- Industry’s first assembly optimizer for fast development and improved parallelization
- 8/16/32-bit data support, providing efficient memory support for a varietyof applicationsTMS320C67x DSP Features and Options
- 40-bit arithmetic options add extra precision for vocoders and othercomputationally intensive applications
- Saturation and normalization provide support for key arithmeticoperations
- Field manipulation and instruction extract, set, clear, and bit counting support common operation found in control and data manipulation applications.
The C67x devices include these additional features:
- Hardware support for single-precision (32-bit) and double-precision(64-bit) IEEE floating-point operations.
- 32 × 32-bit integer multiply with 32-bit or 64-bit result.
- In addition to the features of the C67x device, the C67x+ device is enhanced for code size improvement and floating-point performance. These additional features include: Execute packets can span fetch packets.
- Register file size is increased to 64 registers (32 in each datapath).
- Floating-point addition and subtraction capability in the .S unit.
- Mixed-precision multiply instructions.
- 32-KByte instruction cache that supports execution from both on-chipRAM and ROM as well as from external memory through a VBUSP-basedexternal memory interface (EMIF).
- Unified memory controller features support for flat on-chip data RAM and ROM organizations for zero wait-state accesses from both load store unitsof the CPU.
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