SDCard Interfacing with LPC2148 using SPI Module
SD-Card Interfacing with LPC2148 using SPI Module
Features of SPI Module in LPC2148
- Single complete and independent SPI controller.
- Compliant with Serial Peripheral Interface (SPI) specification.
- Synchronous, Serial, Full Duplex Communication.
- Combined SPI master and slave.
- Maximum data bit rate of one eighth of the input clock rate.
- 8 to 16 bits per transfer
|Pin Name||Type||Pin Description||LPC2148 Pins|
|SCK0||Input / Output||Serial Clock||P0.4|
|MISO0||Input / Output||Master In Slave Out||P0.5|
|MOSI0||Input / Output||Master Out Slave In||P0.6|
|S0SPCR||SPI Control Register. This register controls theoperation of the SPI.||R/W|
|S0SPSR||SPI Status Register. This register shows thestatus of the SPI.||Read Only|
|S0SPDR||SPI Data Register. This bi-directional registerprovides the transmit and receive data for theSPI. Transmit data is provided to the SPI0 bywriting to this register. Data received by the SPI0can be read from this register.||R/W|
|S0SPCCR||SPI Clock Counter Register. This registercontrols the frequency of a master’s SCK0.||R/W|
|S0SPINT||SPI Interrupt Flag. This register contains theinterrupt flag for the SPI interface.||R/W|
SPI Control Register (S0SPCR)
The S0SPCR register controls the operation of the SPI0 as per the configuration bits setting.
|2||BIT FIELD ENABLE||0 ;The SPI controller sends and receives 8 bits of data pertransfer.|
1; The SPI controllert sends and receives the number of bitsselected by bits field (11:8)
|3||CPHA||Clock Phase Control|
0; The data is sampled on first clock edge
1; The data is sampled on second clock edge
|4||CPOL|| Clock Polarity|
0; Serial Clock (SCK) is active High
1; Serial Clock (SCK) is active High
|5||MSTR|| Master mode select.|
0; The SPI operates in Slave mode.0
1 ;The SPI operates in Master mode.
|6||LSBF|| LSB First controls which direction each byte is shifted when transferred.|
0; SPI data is transferred MSB (bit 7) first.
1 ;SPI data is transferred LSB (bit 0) first.
Serial peripheral interrupt enable.
|11-8||BITS FIELD|| When bit 2 of this register is 1, this field controls thenumber of bits per transfer:|
SPI STATUS REGISTER(S0SPSR)-
The S0SPSR register controls the operation of the SPI0 as per the configuration bitssetting.
|3||ABRT||Slave abort. |
When 1, this bit indicates that a slave abort hasoccurred. This bit is cleared by reading this register.
|4||MODF||Mode fault. |
when 1, this bit indicates that a Mode fault error hasoccurred. This bit is cleared by reading this register, then writingthe SPI control register.
When 1, this bit indicates that a read overrun hasoccurred. This bit is cleared by reading this register.
|6||WCOL||Write collision. |
When 1, this bit indicates that a write collision hasoccurred. This bit is cleared by reading this register, thenaccessing the SPI data register.
|7||SPIF||SPI transfer complete flag. |
When 1, this bit indicates when a SPIdata transfer is complete. When a master, this bit is set at theend of the last cycle of the transfer. When a slave, this bit is seton the last data sampling edge of the SCK. This bit is cleared byfirst reading this register, then accessing the SPI data register.
SPI Data Register (S0SPDR)
This bi-directional data register provides the transmit and receive data for the SPI.Transmit data is provided to the SPI by writing to this register. Data received by the SPIcan be read from this register. When a master, a write to this register will start a SPI datatransfer. Writes to this register will be blocked from when a data transfer starts to when theSPIF status bit is set, and the status register has not been read.
|15-8||Data HIGH||If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, someor all of these bits contain the additional transmit and receivebits. When less than 16 bits are selected, the more significantamong these bits read as zeroes.|
SPI Clock Counter Register (S0SPCCR)
- This register controls the frequency of a master’s SCK. The register indicates the number of PCLK cycles that make up an SPI clock.
- The value of this register must always be an even number. As a result, bit 0 must always be 0.
- The value of the register must also always be greater than or equal to 8.
- Note:-Violations of this can result in unpredictable behavior.
SPI (SCLK) Frequency = PCLK / SPCCR Value Max. Freq=1.875 Mhz
|7-0||Counter||SPI0 Clock counter settinng|
SPI Interrupt Register (S0SPINT)
Digital (SD) cards are removable flash-based storage device SD means ‘secure digital’ and MMC means ‘multimedia card.’ You can insert these cards in your media player, PDA or digital camera. Their small size, relative simplicity, low power consumption and low cost make them an ideal solution for many applications.
- SD/MMC cards have their own architecture and signals.
- These are universal low-cost, high-speed data storage cards.
- MMCs work at 20 MHz, while SD cards work at up to 25 MHz's,
- The two memories work in two different modes: SD mode and serial peripheral interface (SPI).
SD-Card Interfacing with LPC2148
SD Memory interfaces to the host point-to-point (in Fig. an ARM microcontroller is the host). This type of interfacing is very popular in the industry. In serial peripheral interface (SPI) mode, you can use following signals of the host:
1. CS: Host to card chip-select signal
2. CLK: Host to card clock signal
3. MOSI (master -out slave-in): Host to card single bit data signal
4. MISO (master - in slave - out ) : Card to host single-bit data signal
Now many companies are manufacturing suitable hosts for the SD bus interface.
For example, Philips is manufacturing LPC2148 microcontroller with MOSI and MISO
•Master-slave mode of communication is used for multiple slave devices in the SD architecture. • MOSI is a unidirectional signal used to transfer serial data from the master to the slave. When the host is master, data can move from the host to the SD card. That’s why MOSI is connected to data input (DI) of the SD/MMC card. •The MISO signal transfers serial data from the slave to the master. When the SD is a slave, serial data is output on MISO signal. When the SD is a master, it clocks in serial data from this signal. •SD memory cards use 1- or 4-bit bus width and star topology to connect multiple cards, while MMC cards use 1-bit bus width and bus topology for reading multiple cards.
Steps to switch from SD-Bus mode to SPI Bus mode of Operation
- All COMMUNICATIONS BETWEEN THE HOST AND THE CARD ARE CONTROLLED BY THE HOST.
- MESSAGES IN THE SPI BUS PROTOCOL CONSIST OF COMMANDS, RESPONSES AND TOKENS.
- THE CARD RETURNS A RESPONSE TO EVERY COMMAND RECEIVED AND ALSO A DATA RESPONSE TOKEN FOR EVERY WRITE COMMAND
- THE SD CARD WAKES UP IN SD CARD MODE, AND it WILL ENTER THE SPI MODE IF ITS CS(Chip Select or Slave Select) LINE IS HELD LOW. WHEN A RESET COMMAND IS SENT TO THE CARD
- THE CARD CAN ONLY BE RETURNED TO THE SD MODE AFTER A POWER DOWN AND POWER UP SEQUENCE THEN THE SPI MODE IS ENTERED.
- THE CARD IS IN THE NONPROTECTED MODE WHERE CRC CHECKING IS NOT USED CRC CHECKING CAN BE TURNED ON AND OFF BY SENDING COMMAND CRC_ON_OFF COMMAND NAME CMD59 TO THE CARD.
Embedded C Program
Function for initializing SPI
PINSEL0=0X00001505;// Select MOSI=P0.6, MISO=P0.5, SCK=P0.4,SSEL=P0.7
S0SPCCR=0X08; // clock is divided by 8 ( SPI Clock freq = PCLK / S0SPCCR Value)
S0SPCR=0X0020; // select as master mode
Function for sending a char
void spi_master(char a)
S0SPDR=a; //write character “a” to be transmitted in S0SPDR
while(!(S0SPSR & 0X80)); // wait till SPIF=1 i.e., complete transfer of data
Function for receiving a char
while(!(S0SPSR & 0X80)); // wait till SPIF=1 i.e., complete reception of data
return S0SPDR; //pick-up received character which is arrived in S0SPDR
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