LPC2148 Interfacing with on-chip (Internal) ADC

Analog Digital Converter in LPC2148


Features of ADC


  • 2 internal  ADC's - ADC0 (6 Channel), ADC1 (8 Channel) 
  • Type: 10-bit, Successive Approximation type, 
  • Supports burst mode (repeated conversion at 3-bit to 10-bit resolution) 
  • Supports simultaneous conversion on both ADC's 
  • Conversion time: 2.44 micro-seconds
  • Start of Conversion by software control / on timer match /transition on a pin 
  • Range: 0 V – VREF (+3.3 V) 
  • Max. clock frequency is 4.5 MHz, (by programming ADC Control (ADxCON Register) 

InternalADC Functional Block Diagram

internal ADC functional block diagram


Block Explanation
BlockSymbolDescriptionI/O
ADC0AD0.1Channel 1P0.28
AD0.2Channel 2P0.29
AD0.3Channel 3P0.30
AD0.4Channel 4P0.25
AD0.6Channel 6P0.4
AD0.7Channel 7P0.5
ADC1AD1.0Channel 0

P0.6

AD1.1Channel 1

P0.8

AD1.2Channel 2

P0.10

AD1.3Channel 3

P0.12

AD1.4Channel 4

P0.13

AD1.5Channel 5

P0.15

AD1.6Channel 6

P0.21

AD1.7Channel 7P0.22

ADC Registers


1) ADxCON - ADC Control Register
  • 32-bit register
  • Useful for Selection of analog input channel, clock frequency to ADC, Resolution, conversion mode, method of issue of SoC, edge for conversion 
RESERVEDEDGESTART--PDN--CLKSBURSTCLKDIVSEL
31-282726-2423-22212019-171615-87-0
Bit     Symbol Description
7-0 SEL
(Channel Selection bits)
 
Select field:- Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 can be one
15-8 CLKDIV: Clock Division factor Value:- The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
16   BURST  0; ADC will not perform Repeated A to D Conversion
1; ADC will perform Repeated A to D Conversion The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed.
  • Remark: START bits must be 000 when BURST = 1 or conversions will not start.
19-17 CLKSClocks:- This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the RESULT bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
CLKS field - 19-18-17No. of Clock cycles used per bit conversion
00011 clocks cycles / 10 bit conversion
00110 clocks/ 9 bits
0109 clocks/ 8 bits
0118 clocks/ 7 bits
1007 clocks/ 6 bits
1016 clocks/ 5 bits
1105 clocks/ 4 bits
1114 clocks/ 3 bits
21    PDN 

Power Down
PDN=1 The A/D converter is operational.
PDN=0 The A/D converter is in power-down mode.

26-24 

 

START
START field - 26-25-24Description
000No start of Conversion
001Start of Conversion Now
27 Edge (In use only when START field contains Values from 010 TO 111)
  • 15-8 CLKDIV: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
    • The A/D Converters on the LPC2148 is also called as The conversion speed is selectable by the user

 A/D Clock frequency= [Pclk/(CLKDIV+1)]  .....................<=4.5 MHz

2) A/D Global Start Register (ADxGSR)
  • Used to initiate simultaneous conversion on both ADCs 
3) A/D Status Register (ADxSTAT)
  • Allows simultaneous checking of status of all A/D channels
  • Contains done, overrun, interrupt flags 
4) A/D Data Registers (ADR0 – ADR7)
  • Contains most recent converted data and EoC(Done) status on respected channel
DONEOVERRUNReserved10 bit A/D RESULTReserved
313029-1615-65-0
5) Global Data Register
  • Contains done bit, most converted data, channel number 
DONEOVERRUN Reserved Channel SelectionReserved10 bit A/D RESULTReserved
3130 29-28-27 26-25-2423-1615-65-0
  • DONE (Bit 31)
    • DONE= 1  ;when an A/D conversion is complete.
    • D0NE=0  ;A/D conversion is in progress

For accurate results, you need to wait until this value is 1 before reading the RESULT bits. (Please note that this value is cleared when you read this register.)

  • OVERRUN (Bit 30)

While not relevant to the examples used in this tutorial, this value with be 1 if the results of one or more conversions were lost when converting in BURST mode. See the User's Manual for further details.  (As with DONE, this bit will be cleared when you read this register.)

  • RESULTS (Bits 15..6)

If DONE is 1 (meaning the conversion is complete), these 10 bits will contain a binary number representing the results of our analog to digital conversion. It works by measuring the voltage on the analog input pin divided by the voltage on the Vref pin.

Analog Input10-bit Digital outputDigital Output in HEX
0V0000 0000 00 B000H
3.3V1111 1111 11 B3FFH

Zero means that the voltage on the analog input pin was less than, equal to or close to GND (Vssa), and 0x3FF (or 0011 1111 1111) indicates that the voltage on the analog input pin was close to, equal to or greater than the the voltage on the Vref pin.  Anything value between these two extremes will be returned as a 10-bit number (between 0 and 1023).  

6) Interrupt Enable Register
  • Enables interrupt on EOC channel
  • Programming ADC registers – Examples (Construction of control words
Examples

  1. Select ADC-0, Channel-1, Clock frequency 3.75 MHz (let PCLK is 15 MHz), burst mode repeated conversion) and 10-bit resolution. Power-up ADC and issue start of conversion.
    Solution: AD0CR    = 0x01210302; // configure SEL, CLKDIV, BURST CLKS & PDN bit fields set START, signal start of conversion
  2. Select ADC–1, Channels 0 to 7, clock frequency 4.5 MHz (assume PCLK is 30 MHz), burst mode repeated conversion, 8-bit resolution.

Interfacing Diagram


ADC interfacing

Embedded C Program for on-chip ADC using interrupt


/*******************************************/
/*Project Name:- ADC in LPC2148 (Using VIC-Interrupt)*/
/*Device:- LPC2148                      */
/*Language:- Embedded C   */
/*Compiler:- KeiluVision4   */
/*For more details visit www.wikinote.org   */
/********************************************/
#include <lpc214x.h>
#include "serial.h"
#include <stdio.h>
void delay(void);
void ADC_ISR(void) __attribute__ ((interrupt("IRQ")));
int adcdata;
float voltage;
unsigned char volt[3];
int i;
int main(void)
{
 PINSEL0 = 0x00000005;
 PINSEL1 = 0x01000000;
 PINSEL2 = 0x00000000;

 Uart0Init();
    Uart0PutS("\n ADC o/p : ");
 AD0INTEN = 0x00000002;       ///On completion of AD conversion channel1 will generate an Interrupt
 VICVectAddr0 = (unsigned int)ADC_ISR;
 VICVectCntl0 = 0x20 | 18;    //// VIRQ and Assign AD0 interrupt Slot0
VICIntEnable = 1 << 18;    ///Enable AD0 interrupt channel of VIC

 AD0CR = 0X01200402; // Channel AD0.1 , Clock 3Mhz, Burst Mode, 11 clocks per 10 bit ,
     //AD conversion is operational, start conversion
  
while(1){
 
  }

return 0;
}

void ADC_ISR()
{
if(AD0DR1 & 0x80000000)    ///Monitor EOC bit from AD Data Register of Channel0
{
  adcdata=(AD0DR1 & 0x0000FFC0);
  adcdata=adcdata>>6;         ///Right shift Digital Result by 6 bits
 voltage=((adcdata/1023.0)*3.3);
  sprintf(volt, "%.1f", voltage);      ////Buffer, decimal value. 1 digit fractional value, float volatage value
 Uart0PutS(volt);    ///print buffer on Hyperterminal  
}
 delay();
 AD0INTEN = 0;       ////Disable ADO Interrupr
VICVectAddr=0;   ///End of ISR
}
void delay(void)
{
int i,j;
for(i=0;i<1000;i++)
for(j=0;j<10000;j++);
}

Embedded C Program for on-chip(Internal ADC) without Interrupt


/**********************************************************/
/*Project Name:- ADC in LPC2148 (Without Using Interrupt)*/
/*Device:- LPC2148                                       */
/*Language:- Embedded C                                  */
/*Compiler:- KeiluVision4                                */
/*For more details visit www.wikinote.org                */
#include<lpc214x.h>
#include<stdio.h>
#include "serial.h"
void delay(void);
int main()
{
int adcdata;
float voltage;
unsigned char volt[3];
 PINSEL0=0X00000000;
 PINSEL1=0X01000000; //Select P0.28 pin function as Analog i/p
Uart0Init();
 AD0CR=0x00210402; ///CHANNEL1 OF ADC0, ad freq=3MHz,
while(1)
 {
 if(AD0DR1 & 0x80000000) ////EOC bit monitoring
 {
   adcdata=(AD0DR1 & 0x0000FFC0);
   adcdata=adcdata>>6;
   voltage=((adcdata/1023.0)*3.3);
   sprintf(volt, "%.1f", voltage);  ADC o/p=1.2
   Uart0PutS("\n ADC o/p : ");
   Uart0PutS(volt);
   delay();
  }   
 }
}
void delay(void)
{
int i,j;
for(i=0;i<1000;i++)
for(j=0;j<10000;j++);
}

Download ADC without Interrupt Project: Click Here 

Download ADC with Interrupt Project: Click Here 

Video Tutorial ADC (Internal) Interfacing with ARM7-LPC2148 Without Interrupt: Keil Software Simulation and O/P



Video Tutorial ADC (Internal) Interfacing with ARM7-LPC2148 using VIC (Interrupt Controller): Keil Software Simulation plus O/P



References


  • nxp datasheet
  • LPC2148 Architecture and Programming - Dr. N. Mathivanan

Last modified: Tuesday, 4 February 2020, 3:55 PM