Serial communication programming for transmission and reception from computer

UART0

Features

  • 16 byte Receive and Transmit FIFOs
  • Register locations conform to ‘550 industry standard.
  • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
  • Built-in fractional baud rate generator with auto-bauding capabilities.
  • Mechanism that enables software and hardware flow control implementation.

Pin description

Pin   Type      Description
RXD0 Input Serial Input: Serial receive data.
TXD0 Output Serial Output: Serial transmit data.

UART1

Features

  • UART1 is identical to UART0, with the addition of a modem interface.
  • 16 byte Receive and Transmit FIFOs.
  • Register locations conform to ‘550 industry standard.
  • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
  • Built-in fractional baud rate generator with autobauding capabilities.
  • Mechanism that enables software and hardware flow control implementation.
  • Standard modem interface signals included with flow control (auto-CTS/RTS) fully
  • supported in hardware (LPC2144/6/8 only).

Pin description

Pin   Type      Description
RXD1 Input Serial Input: Serial receive data.
TXD1 Output Serial Output: Serial transmit data.
CTS1 Input Clear To Send
DCD1 Input Data Carrier Detect
DSR1 Input Data Set Ready
DTR1 Output Data Terminal Ready
RI1 Input Ring Indicator
RTS1 Output Request To Send

UART0

Block Diagram

UART_Block_Diagram


UART Registers and Programming Steps for UART

U0FCR (FIFO Control Register)
  • 8-BIT Byte Addressable register
  • This reg is used to enable TX & RX FIFO functionalities
  • U0FCR=0x07 is like SCON reg
U0FCR FIFO Control Register - - - - - TX FIFO Reset RX FIFO Reset FIFO Enable
U0LCR (Line Control Register)
  • 8-BIT byte addressable register

UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description 

Bit Symbol Value Description Reset Value
1:0


 
Word Length Select


 
00 5 bit character length 0


 
01 6 bit character length
10 7 bit character length
11 8 bit character length
2
 
Stop Bit Select
 
0 1 stop bit 0
 
1 2 stop bits (1.5 if U0LCR[1:0]==00)
3
 
Parity Enable
 
0 Disable parity generation and checking 0
 
1 Enable parity generation and checking
5:4


 
Parity Select


 
00 Odd parity. Number of 1s In the transmitted character and the attached parity bit will be odd. 0


 
01 Even Parity. Number of is in the transmitted character and the attached parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6
 
Break Control
 
0 Disable break transmission 0
 
1 Enable break transmission. Output pin UARTO TXD Is forced to logic 0 when UOLCR[6] Is active high. 
7
 
Divisor Latch Access Bit (DLAB)
 
0 Disable access to Divisor Latch 0
1 Enable access to Divisor Latch

DLAB (Divisor Latch Buffer)

One high-low pulse across DLAB bit indicates baud rate is successfully loaded.

  • DLAB=1  baud rate is loading
  • DLAB=0  After loading baud rate DLAB must be zero.
Baud Rate
U0LCR=0x83 ;//8 bits character length,No parity,1 stop bit,9600 Baud rate
U0LCR=0x03
U0LSR (Line Status Register)
  • 8-bit byte addressable register
  • Consists of different flag bits, TI interrupt & RI interrupt flag bit
UART0 Line Status Register
Bit Symbol Value Description Reset value
0 Receiver Data Ready (RDR)   U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIFO is empty.  0
0 U0RBR is empty.
1 U0RBR contains valid data.
1

 
Overrun Error (OE)

 
  The overrun error condition is set as soon as it occurs. An U0LSR read clears U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled and the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will not be overwritten and the character in the UART0 RSR will be lost.  0

 
0 Overrun error status is inactive.
1 Overrun error status is active.
2
 
Parity Error
 
 

When the parity bit of a received character is in the wrong state, a parity error occurs. An U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR(0).

Note: A parity error is associated with the character at the top of the UART0 RBR FIFO.

0
 
0 Parity error status is Inactive.
3

 
Framing Error (FE)

 
 

When the stop bit of a received character is a logic 0. a framing error occurs. 0 An U0LSR read dears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error.

Note: A framing error is associated with the character at the top of the UART0 RBR FIFO.

0

 
0 Framing error status is inactive. 
1 Framing error status is active. 
4

 
Break Interrupt (BI)

 
 

When RXD0 is held in the spacing state (all 0's) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD0 goes to marking state (all 1s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR(0).

Note: The break interrupt is associated with the character at the top of the UART0 RBR FIFO.

0

 
0 Break interrupt status is inactive. 
1 Break interrupt status is active. 
5

 
Transmitter Holding Register Empty (THRE)

 
  THRE is set immediately upon detection of an empty UART0 THR and is 1
cleared on a U0THR write. 
1

 
0 U0THR contains valid data. 
1 U0THR is empty.
6

 
Transmitter Empty (TEMT) 

 
  TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data. 1

 
0 U0THR and/or the U0TSR contains valid data. 
1 U0THR and the U0TSR are empty. 
7

 
Error in RX FIFO (RXFE) 

 
  UOLSR(7) is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART0 FIFO. 0
 
0 U0RBR contains no UART0 RX errors or U0FCR[0]=0.
1 UART0 RBR contains at least one UART0 RX error.
6th bit of LSR is TI flag bit
While(!(U0LSR&0x40));//Monitoring TI bit syntax

0th bit of LSR is RI flag bit
While(!(U0LSR&0x10));//Monitoring RI bit syntax
DLR (Divisor Latch Register)
  • DLR is 16-bit register
  • Used to load baud rate
  • As the baud rate is 8-bit value, divide DLR into two parts DLM & DLL (8-bit each)

For 9600 baud rate
U0DLL=0x63;     //(Pclk=12Mhz)
U0DLM=0x00

U0DLL:U0DLM=[Pclk/16*Desired Baud rate]

U0THR (Transmit Hold Register)
  • 8-bit byte addressable reg
  • Data can be loading to U0THR, whenever transmitting data

U0THR=‘A’   //THR buffer register is used only for transmitting

U0RBR (UART0 Receive Buffer Register)
  • 8-bit byte addressable reg
  • Data can be loading into U0RBR, whenever receiving data.

a = U0RBR   //RBR buffer register is used only for transmitting

Interfacing Diagram of LPC2148 with PC

Serial-Communication-between-LPC2148-and-PC


OR


 

 

Algorithm

1) Start
2) Initialise UART0 serial interface using following instruction

PINSEL0=0X0000 0005;//Enable P0.0-TxD0,P0.1-RxD0

U0LCR=0X83;  //8-BIT Character lenth,NO parity,1 stop bit, DLAB=1
U0DLL=97; //Baud rate=9600@PCLK=15Mhz
U0LCR=0X03;//DLAB=0
3) LPC2148 will receive characters transmitted by PC

4) LPC2148 will transmit the characters received back to PC

3) Transmit different AT commands through UART module using instruction
while(!(U0LSR&0X20));//Monitor TI flag

4) If transmission buffer is Empty,Transmit single character at a time
U0THR=ch;

5) Provide delay while transmitting each command
6) To transmit a single character use PUTCH function & to transmit a string use PUTS function
7) END

Embedded C program for Serial Transmission and Reception

/**************************************************************************/
/* Project Name:-Serial Communication between PC and LPC2148 using UART Module  */
/* Device:- LPC2148                          */
/* Compiler:- KeiluVision4                   */
/* Language:- Embedded C  */
/* Visit www.wikinote.org for more Details   */
/********************************************************************************************/
#include<lpc21xx.h>   //Includes LPC2148 register definitions

void Uart0Init (void)      // Initialize Serial Interface       
{                   
    PINSEL0 = 0x00000005;           //Enable RxD0 and TxD0                     
   U0LCR = 0x83;                   // 8 bits, no Parity, 1 Stop bit            
   U0DLL = 97;                     // 9600 Baud Rate @ 15MHz PCLK         
   U0LCR = 0x03;       // DLAB = 0  
}
   
void Uart0PutCh (unsigned char ch)  // Write character to Serial Port   
{                    
    U0THR = ch;
  while (!(U0LSR & 0x20));
}

void  Uart0PutS(unsigned char *str)  //A function to send a string on UART0
{  
while(*str)
{  
     Uart0PutCh(*str++);     
}
}
unsigned char Uart0GetCh (void)  // Read character from Serial Port   
{            
 while (!(U0LSR & 0x01));
 return (U0RBR);
}
int main()
{
unsigned char a;
Uart0Init();
while(1)
{
a=Uart0GetCh();
Uart0PutCh(a);
}
}
                                                                                          Download Serial Communication Project : Click Here 

Video Tutorial Plus Keil Simulation


References

  • Created, Edited, Notes by Prof. Sujit Wagh, Sinhgad's SKNCOE, Pune
  • WikiNote Foundation

Last modified: Saturday, 21 September 2019, 3:49 PM