Interrupt Structure

Interrupt Structure

  • ARM7 Processor hardware interrupt inputs: 2, (FIQ. IRQ)
  • LPC2148 external interrupt inputs: 4 (available on 9 pins)
  • Processor and on-chip user peripherals generate interrupts
  • LPC2148 uses ARM PrimeCell (PL190) Vectored Interrupt Controller for managing interrupts.
  • PL190 is interfaced to ARM core through the fast AHB bus

When interrupt occurs:

  1. VIC identifies the source of interrupts
  2. Passes requests on interrupt request pins as per the configuration
  3. If more than one interrupt occurs at a time, VIC resolves priority

Vectored Interrupt Controller (VIC)

  • 32 interrupt request inputs, LPC2148 uses 22 of 32 interrupts
  • Categorizes into Fast Interrupt Request, Vectored IRQ, Non Vectored IRQ interrupts
  • Any of the 22 interrupts can be assigned to FIQ / VIRQ / NVIRQ
  • FIQ: Generally, only one interrupt is assigned, VIC provides ISR address. If more than one is assigned to FIQ, VIC combines all, generates VICFIQ, provides only one ISR address for all FIQ (Non-Vectored FIQ) .
  • VIC has 16 VIRQ slots, Slot-0 to Slot-15. Any IRQ configured interrupts can be assigned to any slot. Priorities are in the order of slot number.
  • Interrupts configured as IRQ, not assigned any VIRQ slot, is assigned as NVIRQ
  • VIRQ & NVIRQ interrupts are combined and VICIRQ is generated
  • Programs can handle 1 FIQ, 16 VIRQ, 1 NVIRQ (total 18) interrupts


VIC Registers (only important listed)

  1. VICIntSelect: High, Low bits select interrupts as FIQ, IRQ respectively
  2. VICIntEnable: High bit enables FIQ or IRQ classified interrupts
  3. VICIntEnClr: High bit disables FIQ or IRQ classified, enabled interrupts
  4. VICSoftInt: Generates any interrupt by software. High bit generates corresponding interrupt
  5. VICSoftIntClr: Clears a bit in Software Interrupt register
  6. VICIRQStatus: A high bit indicates corresponding IRQ classified, enabled IRQ interrupt is active
  7. VICFIQStatus: A high bit indicates corresponding FIQ classified, enabled IRQ interrupt is active
  8. VICVectAddr: Holds ISR addr of active interrupt. Writing any value indicates End of Interrupt
  9. VICVectAddr0 – VICVectAddr15: Hold ISR addresses for slots 0 to 15
  10. VICVectCntl0 – VICVectCntl15: Control 16 IRQ slots, assigns sources to each slot. Bit [4:0] selects VIC channel, bit [5] select VIRQ / NVIRQ, high / low bit provides dedicated / default ISR addr.
Programming VIC registers
  • VICIntSelect: Set / reset the bits for FIQ / IRQ classification
  • VICVectCtrlx: Assign VIRQ slot ‘x’ to IRQ classified interrupt
  • VICVectAddrx: Write ISR addr of VIRQ interrupt assigned to slot ‘x’
  • VICIntEnable: Enable interrupts 
Programming VIC registers: Examples

1) Programming VICIntSelect register

VICIntSelect = 0x0000 0010; // enable VIC Timer-0 channel as VFIQ interrupt  (by default all interrupts are VIRQ enabled) //

2) Programming VICVectCntlx register 

VICVectCntl0=(0x01<<5)|0x04; // assign VIRQ Slot-0 to Timer-0, enable Slot-0  (bit[4:0] is channel no. bit[5] enables slot) //

3) Programming VICVectAddrx register

void Timer0ISR(void) __irq;      // declare prototype for ISR//
unsigned long int T0vectaddr;    // declare variable to hold Timer-0 ISR address//
T0vectaddr=(unsigned)Timer0ISR; // place ISR address in variable//
VICVectAddr0 = T0vectaddr;      // write ISR address into Slot-0 VectAddr reg//

4) Programming VICIntEnable register

VICIntEnable = 0x00000010;    // enable Timer-0 interrupt//

Handling FIQ interrupts

  • Branch instruction at 0x0000001C uses address of FIQ handler directly and goes to FIQ routine. This reduces interrupt latency. 
  • If more than one interrupt are assigned as FIQ, the handler routine identifies the source of interrupt. This increases interrupt latency. 
  • Executes codes respective of identified interrupts. 
  • Clears flags set by peripherals in their interrupt registers o End of interrupt.

Handling IRQ interrupts

  • On interrupt, processor executes branch instruction from interrupt vector table at 0x 00000018 and branches to IRQ handler routine 
  • Reads VICVectAddr reg that holds address of highest priority pending VIRQ Slot-x interrupt. If no slot is assigned, it holds address of default vect address 
  • Branches to handler routine. 
  • Reads interrupt register of the peripheral, identifies actual source, executes codes respective of the interrupt. 
  • Clears interrupt flags set by peripherals in their interrupt registers. 
  • Writes a dummy word into VICVectAddr register to indicate EoI, to clear respective interrupt in VIC interrupt priority hardware. 
  • Returns back to interrupted program, re-enables interrupts.


  • and LPC2148 user manual
  • LPC2148 Architecture and Programming - Dr. N. Mathivanan

Last modified: Thursday, 19 September 2019, 2:19 PM