System Control Block ( PLL and VPB divider)

System Control Block


Phase Locked Loop (PLL)


  • LPC214x has two PLLs: PLL0 and PLL1
  • PLL0 is used to generate clock for CPU (CCLK) & peripherals (PCLK)
  • PLL1 is used for USB
  • It uses crystal oscillator input frequency (FOSC) 10–25 MHz and generates output up to 60 MHz
  • Parameters m & p determine output frequency, CCLK = m x FOSC
  • In the feedback path of PLL there is current controlled osc (CCO) whose frequency should be kept within 156 – 320 MHz.

Computing m and p values for generating CCLK of 60 MHz from FOSC 12 MHz

  • = CCLK/FOSC = 60/12 = 5
  • If p is chosen to be 2, CCO (= 2 x p x 60) is within 156 – 320 MHz.

pll


PLL Registers
  • PLLxCON – Controls PLL activation; used to enable and connect PLL
  • PLLxCFG – Multiplier value (bits [4:0]) and divider value (bits [6:5] are configured
  • PLLxSTAT – Shows current enable & connect status, m & p values, lock status
  • PLLxFEED – Writing feed sequence, i.e. ‘0xAA’ and ‘0x55’ in sequence, to this register– It enables changes made to PLLCON, PLLCFG registers to take effect APBDIV – Sets PCLK freq to 1/4, same or 1/2 of CCLK (by writing 0x00, 0x01, 0x02)
PLL configuration sequence
  1. Determine m and p values for desired CCLK and PCLK from FOSC
  2. Enter (m-1) in bits [4:0] and enter 00/01/10/11 for p values 1/2/4/8 in bits [6:5] of PLLCFG register.
  3. Enable PLL using PLLCON register (by setting bit[0]).
  4. Issue feed sequence, i.e. write constants 0xAA, 0x55 into PLLFEED reg
  5. Wait for PLL to lock (by checking bit[10],
  6. Connect & enable PLL using PLLCON reg. (by setting bits[1:0])
  7. Issue again feed sequence 

Examples

  • Configuring PLL0 for generating 60 MHz CCLK from 12 MHz FOSC multiplier = CCLK / FOSC = 60 / 12 = 5; (m-1) = 4 is placed in bits [4:0]
  • ‘p’  is chosen as 2, since CCO (= 2 x p x 60) is to be within 156 – 300 MHz

PLL_PM_Values


Enabling but not connecting PLL0, enabling and connecting:

  • Bit [0] of PLL0CON register is set for only enabling and bits[1:0] are set for enabling and connecting.
  • PLL0CON    =    0x01;    // enable PLL but not connect
  • PLL0CON    =    0x03;    // enable PLL and connect

Issue of PLL feed sequence:

  • PLL0FEED    =    0xAA;    // first fixed value
  • PLL0FEED    =    0x55;    // second fixed value

Checking PLL0 lock status & waiting till PLL0 locks onto the target frequency:

PLOCK, the bit [10] of PLL0STAT register, is polled and checked for lock status.

PLOCK = 0x40;

while(!(PLLSTAT & PLOCK));  // poll lock status & wait till PLL0 locks

VPB Divider


Programming APB divider for desired PCLK frequency:

Value 0x00, 0x01 or 0x02 in APBDIV register sets the PCLK frequency to one-fourth, same as or half of CCLK frequency.

APBDIV = 0x02    // set PCLK frequency to (CCLK/2)

Important Terms for Solving Numerical Based on PLL

TermsDesciptionValues or Range
FoscOscillator Clock Frequency10 MHz to 60 MHz
CclkCPU Clock Frequency60 Mhz Maximum
PclkPeripheral Clock FrequencyBased on value in VPBDIV register
MMultiplier 1 to 32 (Practically 1 to 6)
PDivider1, 2, 4, 8
FccoCurrent Controlled Oscillator Frequency156 MHz - 320 MHz

Numericals based on PLL


Q.1 ) Explain with neat diagram relation between CCLK & PCLK with the help of VPB Divider.
Find the configuration of VPB Divider for achieving PCLK=30 MHz, for FOSC=12 MHz (March -2018 In-Sem)

Solution -One have to solve this question by reverse engineering.From VPB Divider block
we know the relation between Pclk and Cclk
Given - Pclk = 30 MHz, Fosc= 12 MHz

Assume case-1 

VBDIV =0x00 ; Pclk= (1/4) of Cclk

CCLK = 4 x PCLK = 4 x 30 = 120 Mhz

Actually Cclk = CPU Clock can't be greater than 60 MHz, Hence our assumption is wrong.

Assume case-2

VPBDIV =0x01 ; Pclk= Cclk
CCLK = PCLK = 30Mhz

CCLK= m x Fosc
we get
m=2.5
Actually multiplier (m) must be an integer Value (in the range of 1 to 32 ) but in above claculations it’s fraction. Hence our assumption is wrong

Assume case-3
 if VPBDIV =0x02  then Pclk= (1/2) of Cclk
Therefor, CCLK = 2 x PCLK = 60Mhz
CCLK= m x Fosc
we get
m=5
assume P = divider = 2 (Value of P can be 1,2,4,8)
FCCO=2 x P x CCLK = 240MHZ which is valid in the range 156M hz <  FCCO < 320Mhz

So in Case-3 we gets the value to be loaded in M = 5, and P = 2 and VPBDIV= 0x02
Note- while loading value in M field of PLLCFG register it should be always (M-1)

Q.2 Explain with neat diagram relation between CCLK & PCLK with the help of VPB Divider.
Find the configuration of VPB Divider for achieving PCLK=30 MHz, for FOSC=15 MHz
Find the configuration of VPB Divider for achieving PCLK=30 MHz, for FOSC=15 MHz

Solution - One have to solve this question by reverse engineering.From VPB Divider block
we know the relation between Pclk and Cclk
Given - Pclk = 30 MHz, Fosc= 15 MHz

Assume case-1 

VBDIV =0x00 ; Pclk= (1/4) of Cclk

CCLK = 4 x PCLK = 4 x 30 = 120 Mhz

Actually Cclk = CPU Clock can't be greater than 60 MHz, Hence our assumption is wrong.

Assume case-2

VPBDIV =0x01 ; Pclk= Cclk
CCLK = PCLK = 30Mhz

CCLK= m x Fosc
we get
m=2
assume P = divider = 4 (Value of P can be 1,2,4,8)
FCCO=2 x P x CCLK = 240MHZ which is valid in the range 156M hz <  FCCO < 320Mhz
 

So in Case-2 we gets the value to be loaded in M = 2, and P = 4 and VPBDIV= 0x02
Note- while loading value in M field of PLLCFG register it should be always (M-1)

Assume case-3
 if VPBDIV =0x02  then Pclk= (1/2) of Cclk
Therefor, CCLK = 2 x PCLK = 60Mhz
CCLK= m x Fosc
we get
m = 4
assume P = divider = 2 (Value of P can be 1,2,4,8)
FCCO=2 x P x CCLK = 240MHZ which is valid in the range 156M hz <  FCCO < 320Mhz

So in Case-3 we gets the value to be loaded in M = 5, and P = 2 and VPBDIV= 0x02
Note- while loading value in M field of PLLCFG register it should be always (M-1)

 

References


  • WikiNote Foundation

Last modified: Thursday, 19 September 2019, 1:59 PM