ARM and RISC Design Philosophy

ARM and RISC Design Philosophy

RISC Processors

¨It is a design philosophy aimed at delivering simple but powerful instruction set that executes within a single cycle at high clock speed.

  • RISC is an acronym for Reduced Instruction Set Computers
  • CISC – Complex Instruction Set Computer

The RISC Design Philosophy

  • CISC and RISC differ in complexities of their instruction sets where CISC is more complex than RISC.
  • Concentrates on reducing the complexity of instructions performed by the hardware to provide greater flexibility and intelligence in software.
  • The smaller instruction set allows a designer to implement a hardwired control unit which runs at a higher clock rate than its equivalent micro sequenced control unit.

RISC design

The RISC Philosophy (Four major Rules)

Rule 1. Instructions
  • Reduced number of instruction classes to provide simple operations that can each execute in a single cycle.
  • Each instruction is a fixed length to allow the pipeline to fetch future instructions before decoding the current instruction. (Unlike CISC)
Rule 2. Pipelines
  • The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines.
  • Ideally, the pipeline advances by one step on each cycle for maximum throughput. Instructions can be decoded in one pipeline stage.
Rule 3. Registers
  • RISC machines have a large general-purpose register set.
  • Any register can contain either data or an address.

(CISC: Have dedicated registers for specific purposes)

Rule 4. Load-Store Architecture
  • The processor operates on data held in registers.
  • Separate load and store instructions: transfer data between the register bank and external memory. Because memory accesses are costly.

ARM architecture improvements over RISC

  1. Variable cycle execution for certain instructions: Not every ARM instruction executes in a single cycle.
  2. Inline barrel shifter leading to more complex instructions: The inline barrel shifter is a hardware component that preprocesses one of the input registers before it is used by an instruction. This expands the capability of many instructions to improve core performance and code density.
  3. Thumb Instruction Set: ARM has enhanced the processor core by adding a second 16 bit instruction set called Thumb. This thumb instruction permits the ARM core to execute either 16 bit or 32 bit instructions. The 16 bit instructions improve code density by about 30 percent compare to 32 bit instructions of fixed length.
  4. Conditional execution: An instruction is only executed when a specific condition has been satisfied. This feature improves performance and code density by reducing branch instructions.
  5. Enhanced instructions: The enhanced digital signal processor (DSP) instructions were added to the standard ARM instruction set to support fast 16 x 16-bit multiplier operations and saturation. These instructions allow a faster-performing ARM processor in some cases to replace the traditional combinations of a processor plus a DSP.

RISC vs CISC

RISC CISC

Simple instruction taking one cycle.

1.Complex instruction may take one or more clock cycles.

Large symmetric register file

Few registers to store data.

Fewer instructions to access memory.

More instructions to access memory

1.Few addressing modes.

More addressing modes

Instruction Decoder is simple. Hardwired logic is used for the decoder.

The instruction decoder is complex. A decoder using ROM which consists microcode.

Supports pipelining. i.e. overlapping of fetch, decode, execute takes place.

Does not support pipelining.

Fixed instruction size.

Variable instruction size.

Core takes less chip area so more space for cache, MMU.

More chip area is taken by core CPU.

Complexity in software. Compiler design is difficult Complexity in Hardware.  Emphasis is on hardware

Higher clock rates. So faster.

Lower clock rates. So, comparatively slower.

Cache memory is present.

Cache memory is absent or unified cache is present

Last modified: Monday, 23 March 2020, 6:41 PM