ARM7 Programmer's Model or Register Model
- In total 17(Visible)+20(Banked Rrgisters)=37
- The active registers available in the user mode are shown below.
- This is protected mode which is normally used while executing applications.
- 16 Data registers & one status register
- r0 to r13 are orthogonal general purpose register.
- Orthogonal means, any instruction that you can apply to ro can equally be applied to any of the other register.
- Eg. ADD ro, r1, r2
- ADD r5, r6, r7
- R13 (stack pointer) and stores the top of the stack in the current processor mode.
- R14(LR) Link Register where the core puts the return address on executing a subroutine.
- R15(PC) Program counter stores the address of next instruction to be executed.
- In ARM state all ARM instruction are 32-bits wide.
- In Thumb state all instructions are 16-bit wide.
- In ARM state Instruction have to be four byte aligned in the memory. Which implies that the bottom two bits of the PC are always zero(Memory location 1000H,1004,1008H).
CPSR: Current Processor Status Register
- ARM core uses CPSR to moniter & control internal operations.
- The unused part reserved for future expansion.
- CPSR fields is divided in to four fields, each 8-bits wide: flags, status, extension, and control.
- In current designs status & extension fields are reserved for for future purpose.
- In some ARM processor cores have extra bits allocated J bit (available only on Jazelle enabled processing which execute 8-bit instructions).
|Flag bit||Sets when|
In case of signed no. operations If result
MSB=1 ;Indicates the result of operation is NEGATIVE
|Z- Zero||The result of operation is zero|
|C- Carry||The result causes an unsigned carry(carry out of MSB)|
|V-Overflow||The result causes a signed overflow|
|Q- Saturation||The result causes an overflow or saturation|
|I- Interrupt request Disable||If set interrupt request channel is disabled|
|F- Fast interrupt request Disable||If set fast interrupt request channel is disabled|
|J- Jazelle instruction set||If set processor will execute Jazelle instructions|
|T-Thumb instruction set||If set processor will execute Thumb Instruction set|
SPSR: Save Program Status Register
Suppose Processor is in USER mode of operation and if IRQ request arrives then processor has to switch itself to IRQ mode of operation but at the same after serving IRQ mode processor should return to USER mode and should resume its working.
So current processor status is copied into SPSR from CPSR in order to resume back.
Difference ARM & Thumb Instruction Set
ARM processor core can support 3 instruction sets. These are
1. ARM Instruction set
2. Thumb Instruction set
3. Jazelle Instruction Set
By default it executes ARM Instruction set
|Parameters||ARM Instruction Set||Thumb Instruction Set|
|How Processor Executes?||By default Processor Executes|
T=0, from CPSR Register
|T=1, from CPSR register|
|Instruction Size / Width||32-bit||16-bit|
|No. of CPU instructions||58||30|
|Conditional Execution of Instructions||Almost all instructions get conditionally executed||Only branch Instructions are get conditionally executed|
|Data Processing Instructions||Access to Barrel shifter and ALU||Separate barrel shifter and ALU instructions|
|Program Status Register Access||Read & Write access in privilleged mode||No direct access|
|Register uses||15 General Purpose Register + PC||8 General Purpose+ 7 High Purpose + PC|
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