ARM7, ARM9 & ARM11 features, advantages & suitability in embedded application

ARM7 Processor Family


Introduction


  • It is introduced in 1994 (ARM7TDMI, ARM7EJ-S, ARM720T)
  • Arm7 family has been immensely successful & has established ARM as the architecture of choice in digital word.
  • Over the years more than 10 billion ARM7 processor family based devices have powered a verity of cost & power sensitive applications.
  • Now a days never embedded designs are making use of latest ARM processor such as Cortex-M0 & Cortex-M3.

Note: The ARM7 processor family ( ARM7 TDMI) is not recommended for new designs.

Features of ARM7


  1. Pipeline Depth: 3 stage (Fetch, Decode, Execute)
  2. Operating frequency: 80 MHz
  3. Power Consumption: 0.06  mW/MHz.
  4. MIPS/MHz: 0.97
  5. Architecture used: Von-Neumann
  6. MMU/MPU: Not present
  7. Cache Memory: Not present
  8. Jazelle Instruction: Not present
  9. Thumb Instruction: Yes (16 bit instruction set)
  10. ARM Instruction set: Yes (32 bit)
  11. ISA (Instruction Set Architecture): V4T (4 TH Version)
  12. Interrupt Controller: Not Present 
  13. ISR entry: Non Deterministic ISR entry
  14. Power Management: No in built Power Management 
  15. Instruction Set Performance v/s code size: Optimal performance code size balance requires interworking between ARM & Thumb code
  16. Ease of application porting from one device to another: Lack of standardization inhibits application porting

ARM9 Processor Family


Introduction


  • This family enables single processor solution for microcontroller, DSP & JAVA applications, offering savings in chip area & complexity, power consumption & time to market
  • ARM9 – enhanced processors are well suited for applications requiring a mix of DSP+ Microcontroller performance 
  • ARM9 family includes – ARM926EJ-S, ARM946E-S, & ARM968E-S processors.

Features of ARM9


  1. Pipeline Depth: 5 stage (Fetch, Decode, Execute, Decode, Write)
  2. Operating frequency: 150 MHz
  3. Power Consumption: 0.19 mW/MHz
  4. MIPS/MHz: 1.1
  5. Architecture used: Harvard
  6. MMU/MPU: Present
  7. Cache Memory: Present (separate 16k/8k)
  8. ARM/ Thumb Instruction: Support both
  9. ISA (Instruction Set Architecture): V5T(ARM926EJ-S)
  10. 31 (32-Bit size) Registers
  11. 32-bit ALU & Barrel Shifter
  12. Enhanced 32- bit MAC block
  13. Memory Controller
    Memory operations are controlled by MMU or MPU
    1. MMU:
      • Provides Virtual Memory Support
      • Fast Context Switching Extensions
    2. MPU:
      • Enables memory protection & bounding 
      • Sand – boxing of applications
  14. Flexible Cache Design (sizes can be 4KB to 128KB)
  15. Flexible Core Design
  16. DSP Enhancements: (very important)
  17. Single cycle 32x16 multiplier Implementation 
  18. Speed up all the multiply instructions
  19. New 32x16 & 16x16 multiply instructions
  20. Allows independent access to 16 bit halves of registers
  21. ARM ISA supports 32x32 multiply instruction
  22. Saturating Arithmetic (QADD, QSUB)
  23. Count leading zero for factor Division

Applications of ARM9


  1. Consumer type: Smart phones, PDA, Set-Top box, Electronics Toys, Digital Cameras, etc.
  2. Networking type: Wireless LAN, 802.11, Bluetooth, etc.
  3. Automatic: Power Train, ABS, Navigation, etc.
  4. Embedded USB controllers, Bluetooth controllers, Medical scanners, etc.
  5. Storage: HDD controllers, solid state drivers etc.

ARM11 Processors Family


Introduction


  • This family provides the engine that power many smartphones, also widely used in consumer, home & embedded applications.
  • It delivers low power & a range of performance from 350MHz to 1GHz.
  • ARM11 processor software is compatible with all previous generations of ARM processors.
  • It introduces 32-bit SIMD for  media processing
    • Physically tagged caches to improve OS context switch performance.
    • Trust zone for H/W enforced security.
    • Tightly coupled memories for real-time applications.
  • ARM11 family includes 
  • ARM1176JZ (F)-S & ARM11MP core, ARM1136J(F)-S, ARM1156T2-S processor.

Features of ARM11


  1. Pipeline Depth: 8stage 
  2. Operating frequency: 335MHz.
  3. Power Consumption: 0.4mW/MHz.
  4. MIPS/MHz: 1.2
  5. Architecture used: Harvard
  6. MMU/MPU: Present
  7. Multiplier unit: 16x32 (16 bits of 32-bit size register)
  8. Cache Memory: present (4-64k size)
  9. ISA (Instruction Set Architecture): V6
  10. Enhanced multiply instruction & saturation
  11. Powerful ARMV6 instruction set architecture
  12. Supports the thumb instruction set-memory BW & Size requirements reduces by up to 35%
  13. Supports Jazelle Technology for efficient embedded JAVA execution
  14. Supports the DSP extensions
  15. SIMD media processing extensions deliver up to 2x performance for video processing
  16. ARM Trust-Zone Technology for on chip security
  17. Thumb-2 Technology for enhanced performance energy efficiency & code density
  18. Low power consumption
  19. High performance integer processor
  20. Vectored interrupt interface & low-interrupt latency mode speeds up interrupt response & real time performance
  21. Optional vector floating point co-processor for automotive/ industrial controls & 3D graphics acceleration

References


  • ARM website www.arm.com
  • Created, Edited, Developed and Notes by Prof Sujit Wagh, Sinhgad's SKNCOE, Vadgaon Bk, Pune
  • WikiNote Foundation

Last modified: Thursday, 19 September 2019, 1:27 PM