ARM7, ARM9 & ARM11 features, advantages & suitability in embedded application
ARM7 Processor Family
- It is introduced in 1994 (ARM7TDMI, ARM7EJ-S, ARM720T)
- Arm7 family has been immensely successful & has established ARM as the architecture of choice in digital word.
- Over the years more than 10 billion ARM7 processor family based devices have powered a verity of cost & power sensitive applications.
- Now a days never embedded designs are making use of latest ARM processor such as Cortex-M0 & Cortex-M3.
Note: The ARM7 processor family ( ARM7 TDMI) is not recommended for new designs.
Features of ARM7
- Pipeline Depth: 3 stage (Fetch, Decode, Execute)
- Operating frequency: 80 MHz
- Power Consumption: 0.06 mW/MHz.
- MIPS/MHz: 0.97
- Architecture used: Von-Neumann
- MMU/MPU: Not present
- Cache Memory: Not present
- Jazelle Instruction: Not present
- Thumb Instruction: Yes (16 bit instruction set)
- ARM Instruction set: Yes (32 bit)
- ISA (Instruction Set Architecture): V4T (4 TH Version)
- Interrupt Controller: Not Present
- ISR entry: Non Deterministic ISR entry
- Power Management: No in built Power Management
- Instruction Set Performance v/s code size: Optimal performance code size balance requires interworking between ARM & Thumb code
- Ease of application porting from one device to another: Lack of standardization inhibits application porting
ARM9 Processor Family
- This family enables single processor solution for microcontroller, DSP & JAVA applications, offering savings in chip area & complexity, power consumption & time to market
- ARM9 – enhanced processors are well suited for applications requiring a mix of DSP+ Microcontroller performance
- ARM9 family includes – ARM926EJ-S, ARM946E-S, & ARM968E-S processors.
Features of ARM9
- Pipeline Depth: 5 stage (Fetch, Decode, Execute, Decode, Write)
- Operating frequency: 150 MHz
- Power Consumption: 0.19 mW/MHz
- MIPS/MHz: 1.1
- Architecture used: Harvard
- MMU/MPU: Present
- Cache Memory: Present (separate 16k/8k)
- ARM/ Thumb Instruction: Support both
- ISA (Instruction Set Architecture): V5T(ARM926EJ-S)
- 31 (32-Bit size) Registers
- 32-bit ALU & Barrel Shifter
- Enhanced 32- bit MAC block
- Memory Controller
Memory operations are controlled by MMU or MPU
- Provides Virtual Memory Support
- Fast Context Switching Extensions
- Enables memory protection & bounding
- Sand – boxing of applications
- Flexible Cache Design (sizes can be 4KB to 128KB)
- Flexible Core Design
- DSP Enhancements: (very important)
- Single cycle 32x16 multiplier Implementation
- Speed up all the multiply instructions
- New 32x16 & 16x16 multiply instructions
- Allows independent access to 16 bit halves of registers
- ARM ISA supports 32x32 multiply instruction
- Saturating Arithmetic (QADD, QSUB)
- Count leading zero for factor Division
Applications of ARM9
- Consumer type: Smart phones, PDA, Set-Top box, Electronics Toys, Digital Cameras, etc.
- Networking type: Wireless LAN, 802.11, Bluetooth, etc.
- Automatic: Power Train, ABS, Navigation, etc.
- Embedded USB controllers, Bluetooth controllers, Medical scanners, etc.
- Storage: HDD controllers, solid state drivers etc.
ARM11 Processors Family
- This family provides the engine that power many smartphones, also widely used in consumer, home & embedded applications.
- It delivers low power & a range of performance from 350MHz to 1GHz.
- ARM11 processor software is compatible with all previous generations of ARM processors.
- It introduces 32-bit SIMD for media processing
- Physically tagged caches to improve OS context switch performance.
- Trust zone for H/W enforced security.
- Tightly coupled memories for real-time applications.
- ARM11 family includes
- ARM1176JZ (F)-S & ARM11MP core, ARM1136J(F)-S, ARM1156T2-S processor.
Features of ARM11
- Pipeline Depth: 8stage
- Operating frequency: 335MHz.
- Power Consumption: 0.4mW/MHz.
- MIPS/MHz: 1.2
- Architecture used: Harvard
- MMU/MPU: Present
- Multiplier unit: 16x32 (16 bits of 32-bit size register)
- Cache Memory: present (4-64k size)
- ISA (Instruction Set Architecture): V6
- Enhanced multiply instruction & saturation
- Powerful ARMV6 instruction set architecture
- Supports the thumb instruction set-memory BW & Size requirements reduces by up to 35%
- Supports Jazelle Technology for efficient embedded JAVA execution
- Supports the DSP extensions
- SIMD media processing extensions deliver up to 2x performance for video processing
- ARM Trust-Zone Technology for on chip security
- Thumb-2 Technology for enhanced performance energy efficiency & code density
- Low power consumption
- High performance integer processor
- Vectored interrupt interface & low-interrupt latency mode speeds up interrupt response & real time performance
- Optional vector floating point co-processor for automotive/ industrial controls & 3D graphics acceleration
- ARM website www.arm.com
- Created, Edited, Developed and Notes by Prof Sujit Wagh, Sinhgad's SKNCOE, Vadgaon Bk, Pune
- WikiNote Foundation
Last modified: Thursday, 19 September 2019, 1:27 PM