Capture mode of CCP
Capture Compare PWM Module
PIC18F2420/2520/4420/4520 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 40/ 44-pin devices, CCP1 is implemented as an Enhanced CCP module with standard Capture and Compare modes and Enhanced PWM modes.The capture and compare operations described in this chapter apply to all standard and Enhanced CCP modules.
|5||DCBx1 PWM mode: This bit is LSB (bit 1) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL|
|4||DCBx0 PWM mode: This bit is LSB (bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL|
|3-0||CCPx Module Mode Select bits|
CCP Module Configuration
- Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable.
CCP MODULES AND TIMER RESOURCES
|CCP/ECCP Mode||Timer Resource|
|Capture||Timer1 or Timer3|
|Compare||Timer1 or Timer3|
Capture Mode Block Diagram
Explanation of Capture Mode Block Diagram
In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the corresponding CCPx pin.
An event is defined as one of the following:
- every falling edge
- every rising edge
- every 4th rising edge
- every 16th rising edge
The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value
CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit.
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation will not work. The timer to be used with each CCP module is selected in the T3CON register
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode
There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter.