Timer2 and It's Programming
The Timer2 module timer incorporates the following features:
- 8-Bit Timer and Period registers (TMR2 and PR2, respectively)
- Readable and writable (both registers)
- Software programmable prescaler (1:1, 1:4 and 1:16)
- Software programmable postscaler (1:1 through 1:16)
- Interrupt on TMR2 to PR2 match
- Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register (Register13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure.
T2OUTPS<3:0>: Timer2 Output Postscale Select bits
|2||TMR2ON: Timer2 On bit|
|1-0|| T2CKPS<1:0>: Timer2 Clock Prescale Select bits|
Timer2 Block Diagram
- In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
- A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by16 prescale options; these are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>).
- The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
- When the two values match, the comparator generates a match signal as the timer output.
- This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler.
- The TMR2 and PR2 registers are both directly readable and writable.
- The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh.
- Both the prescaler and postscaler counters are cleared on the following events:
- a write to the TMR2 register
- a write to the T2CON register
- any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset)
- TMR2 is not cleared when T2CON is written.
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>).
The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>).
The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode.
Timer2 can optionally be used as the shift clock source for the MSSP module operating in SPI mode.
Additional information is provided in Section “Master Synchronous Serial Port (MSSP) Module”.
- Created, Edited and Notes by Prof. Sujit Wagh, SKNCOE, Pune
- WikiNote Foundation