Power Down Modes and Configuration Bit Settings

Power Saving Modes of PIC

Power Management Features

  • Run: CPU on, Peripherals on
  • Idle: CPU off, Peripherals on
  • Sleep: CPU off, Peripherals off
  • Ultra Low 50nA Input Leakage
  • Run mode Currents Down to 11 μA Typical
  • Idle mode Currents Down to 2.5 μA Typical
  • Sleep mode Current Down to 100 nA Typical
  • Timer1 Oscillator: 900 nA, 32 kHz, 2V
  • Watchdog Timer: 1.4 μA, 2V Typical
  • Two-Speed Oscillator Start-up

PIC18F2420/2520/4420/4520 devices offer a total of seven operating modes for more efficient powermanagement. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
There are three categories of power-managed modes:

  • Run modes
  • Idle modes
  • Sleep mode

These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several power saving features offered on previous PIC devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped.

Selecting Power-Managed Modes

Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table

power saving mode op pic18

Clock Sources

The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are:

  • Primary clock, as defined by the FOSC<3:0> Configuration bits
  • Secondary clock (the Timer1 oscillator)
  • Internal oscillator block (for RC modes) 

Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in  “Clock Transitions and Status Indicators” and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.


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Last modified: Tuesday, 17 September 2019, 12:35 PM