Program and Data memory organization

Internal Program and Data memory of PIC18 & it's organization

There are three types of memory in PIC18 enhanced microcontroller devices:

  • Program Memory
  • Data RAM
  • Data EEPROM

As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”.

Program Memory (PROM) Organization

  • PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space.
  • Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).
  • The PIC18F2420 and PIC18F4420 each have 16Kbytes of Flash memory and can store up to 8,192 single-word instructions.
  • The PIC18F2520 and PIC18F4520 each have 32Kbytes of Flash memory and can store up to 16,384 single-word instructions.
  • PIC18 devices have two interrupt vectors.
    • The Reset vector address is at 0000h
    • Interrupt vector addresses are at 0008h and 0018h.
  • The program memory map for PIC18F2420/2520/ 4420/4520 devices is shown in Figure 

program memory organization

Fig. Program Memory Organization In PIC18Fxxxx Microcontroller 


The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 

Data Memory (RAM) Organization

The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2420/ 2520/4420/4520 devices implement all 16 banks. Figure  shows the data memory organization for the PIC18F2420/2520/4420/4520 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR.  “Access Bank” provides a detailed description of the Access RAM

  •  Data Memory up to 4k bytes
  • Data register map  - with 12bit address bus  000-FFF
  • Divided into 256-byte banks
  • There are total of F banks
  • Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected

data memory organization

Data Memory with Access Banks

data memory access bank

Accessing Data Memory

accessing data memory

 The machine code for a PIC18 instruction has only 8 bits for a data memory address which needs 12 bits. The Bank Select Register (BSR) supplies the other 4 bits.
Three ways to access data registers:

  • Direct using Bank Select Registers (BSR)
    • Bank address (4-bit) + Instruction (8-bit)
  • Indirect using File Select Registers (FSR)
    • FSR contains the address of the data register
    • Hence, MPU uses FSR
  • Access Bank using General Purpose Registers (GPR)


  • Created, Edited and Notes by Prof. Sujit Wagh, SKNCOE, Pune
  • WikiNote Foundation

Last modified: Monday, 16 September 2019, 5:09 PM