ADC Interfacing with 8051

Introduction to ADC


  • IN0-IN7: Analog Input channels
  • D0-D7: Data Lines
  • A, B, C: Analog Channel select lines; A is LSB and C is MSB
  • OE: Output enable signal
  • ALE: Address Latch Enable
  • EOC: End of Conversion signal
  • Vref+/Vref-: Differential Reference voltage input
  • Clock: External ADC clock input
Table:-ADC Input channel Selection using Adress Select lines
C(MSB)BA(LSB)ADC input channel to be selected
000IN0
001IN1
010IN2
011IN3
100IN4
101IN5
110IN6
111IN7

 

ADC Timing Diagram


Algorithm for Interfacing

Refer Timing Diagram above

  • Select the channel to which input is to be applied(Using Channel select lines A,B,C)
  • Latch the address by generating LOW-to-HIGH pulse on pin ALE
  • Iniatiate analog to digital conversion  by generating LOW-to-HIGH pulse on pin SOC(Start of conversion)
  • Keep monitoring EOC pin,initially its HIGH,if the A to D conversion is complete it, the EOC pin becomes LOW
  • Take down digital converted data out of ADC, by generating LOW-to-HIGH pulse on pin OE (Output Enable)

Interfacing Diagram


Interfacing Diagram for ADC with 80511

Assembly Language Program for Interfacing

Edit
ORG 00h
ALE BIT P2.6
OE BIT P2.5
SOC BIT P2.6
EOC BIT P2.7
ADDR_A BIT P2.0
ADDR_B BIT P2.1
ADDR_C BIT P2.2
MYDATA EQU P1
ORG 00H
MOV MYDATA,#0FFH
SETB EOC
CLR ALE
CLR SOC
CLR OE
BACK:
CLR ADDR_C
CLR ADDR_B
CLR ADDR_A
ACALL DELAY
SETB ALE
ACALL DELAY
SETB SOC
ACALL DELAY
CLR ALE
CLR SOC
HERE:JB EOC,HERE
HERE1:JNB EOC,HERE1
SETB OE
ACALL DELAY
MOV A,MYDATA
CLR OE
ACALL CONVERSION
ACALL DISPLAY
SJMP BACK

References

  • Created and Developed  by Prof. S.M.Wagh,SKNCOE And Prof.H.Lokhande, Sinhgad's NBNSTIC , Pune
  • WikiNote Foundation

Footnotes

  1. ^ Image by Jayesh Gopal, SKNCOE, Pune

Last modified: Tuesday, 17 September 2019, 3:30 PM