7-segment multiplexed display
Interfacing of multiplexed 7-Segment Display with 8051
About Seven Segment Display
A seven segment display is the most basic electronic display device that can display the digits from 0-F (hexadecimal numbers). The seven segment pins (a,b,c,d,e,f,g) plus the decimal point of a common anode display are connected to port pins of LPC1768 via current limiting resistors (220 Omega). The program is developed using software to display hexadecimal numbers 0-F on the display.
Seven segment LED is device having seven light emitting diodes with either anode terminals (common anode ) or cathode terminals connected together to form a number '8' pattern as shown in the picture.
To use them you should know the pin configuration of the commercially available displays. As you must have guessed these displays should have nine pins( one for each segment + decimal point +common) but the available modules have two pins for common ground. They are internally connected. So they have total of 10 pins.
A 7-Segment display has 7-segments/pins named as a, b, c, b, e, f, g for forming the '8' pattern and and another segment/pin called 'h' for DP (decimal point) along with two extra pins for GND (in case of common cathode).
To display numbers in seven-segment display, it is necessary to define the control signals. Below table shows the segment control for characters 0-9 as required for displaying numbers.
|Segment Control table for displaying characters 0 to 9|
Video Proteus simulation
ALP for the interfacing
Program:- Draw an interfacing diagram of multiplexed 7-segment display and write an ALP to count till 9 with step delay of 1 milliSec. Use (Timer0, Mode 1) for delay generation
- Timer0, Mode 1 i.e. 16-bit mode
- XTAL i.e. fosc = 11.0592 MHz (Assume if not given which is fix in case of 8051)
- Delay to be generated of 1 milliSecond.
Delay Generation Calculations
Crystal Freq = 11.0592 MHz
Internally Timer Module divides this Crystal frequency by the factor of 12 to generate 1 machine cycle frequency ,
Therefor 1 machine cycle frequency = Crystal frequeny / 12
=11.0592 MHz / 12
= 921.6 KHz
Hence T = 1 / 921.6 KHz = 1.08 microSeconds
i.e. 1 machine cycle generates delay of = 1.08 microSeconds
As we have to generate delay of 1 milliSeconds and we are using Timer0 in mode1 i.e 16-bit Timer,
Hence it can count maximum machine cycles of 65535 + 1 machine cycle of overflow =65536
Therefor Number of Machine cycles required to generate delay of 1 milliSeconds are = 925.9 i.e 926 Machine cycles
Initial Value to be loaded in Timer Registers = Final Value + 1 - number of Machine cycles required
= 65535 +1 - 926
= FC62 Hexadecimal
Hence Value to be loaded in TL0= 62 H, TH0= 0FC H
START:MOV R1,#10;Count for displaying numbers from 0 to 9
MOV DPTR,#400H ;DPTR pointing at satrt address of look-up table
MOVC A,@A+DPTR ;Load A with value present at location 400h
MOV P1,A ;send the data to 7-segment display
ACALL DELAY ; call delay
INC DPTR ; increment DPTR
DJNZ R1,BACK ;Decrement R1 by 1 and repeat until becomes 0
Delay:Mov TMOD,#01H //Timer0 in Mode1
Mov TL0,#62H //Load TL0 with Initial value
Mov TH0,#0FCH //Load TH0 with Initial value
SETB TR0 //Start Timer0
Here:JNB TF0,Here //Monitor Timer0 Overflow flag
CLR TF0 //Clear Timer0 Overflow flag
CLR TR0 //Stop Timer0
8051 interfacing with multiplexed 7 segment display
Draw an interfacing diagram of multiplexed 7-segment display and write an ALP to 99 with step delay of 1 milliSec (Timer0, Mode 1)
- Created and developed by Prof S.M.Wagh , SKNCOE and Prof.H.Lokhande, Sinhgad's NBNSTIC, Pune
- Interfacing diagram by Jayesh Gopal, Wikinote volunteer, SKNCOE
- WikiNote Foundation