Interrupt Structure in 8051
- An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.
- Interrupts verses Polling: A single microcontroller can serve several devices. There are two ways to do that:
- The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler
Steps in Executing an Interrupt
- Finishes current instruction and saves the PC on stack.
- Jumps to a fixed location in memory depending on the type of interrupt.
- Starts to execute the interrupt service routine until RETI (return from interrupt)
- Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get POP PC from stack.
Interrupt Vector Table
- Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.
- It is the set of memory locations set aside in the program memory which points at the ISR of different interrupts
Interrupt Service Routine
- It is the program associated with the perticular interrupt whose starting memory location is pointed by IVT table address.
The following table shows interrupt vector table:
|Type of Interrupt||PROM location|
|External Interrupt 0||0003H|
|Timer 0 Overflow||000BH|
|External Interrupt 1||0013H|
|Timer 1 Overflow||001BH|
|Serial Communication Interrupt||0023H|
|Timer 2 Overflow (8052+)||002BH|
|Note: That there are only 8 memory locations between vectors.|
Interrupt Enable (IE) registerAll interrupt are disabled after reset. We can enable and disable them by Interrupt Enable (IE) register.
|Functional name||Bit number||Function|
|EA||IE.7||Disables all interrupts|
|-||IE.6||No implemented,Reserve for future|
|ET2||IE.5||Enables or disables Timer 2 overflow flag interrupt|
|ES||IE.4||Enables or disables Serial communication interrupt|
|ET1||IE.3||Enables or disables Timer 1 overflow flag interrupt|
|EX1||IE.2||Enables or disables Timer 2 overflow flag interrupt|
|ET0||IE.1||Enables or disables Timer 2 overflow flag interrupt|
|EX0||IE.0||Enables or disables Timer 2 overflow flag interrupt|
Enabling and disabling an interrupt
- By bit operation; recommended in the middle of program.
SETB EA ;Enable All
SETB ET0 ;Enable Timer0 ovrflow
SETB ET1 ;Enable Timer1 ovrflow
SETB EX0 ;Enable INT0
SETB EX1 ;Enable INT1
SETB ES ;Enable Serial port
- By mov instruction; recommended in the initial section of program.
MOV IE, #10010110B
A 10 KHz square wave with 50% duty cycle:
ORG 0 ;Reset entry poit
LJMP MAIN ;Jump above interrupt
ORG 000BH ;Timer 0 interrupt vector
T0ISR:CPL P1.0 ;Toggle port bit
RETI ;Return from ISR to Main program
ORG 0030H ;Main Program entry point
MAIN: MOV TMOD,#02H ;Timer 0, mode 2
MOV TH0,#-50 ;50 us delay
SETB TR0 ;Start timer
MOV IE,#82H ;Enable timer 0 interrupt
SJMP $ ;Do nothing just wait
Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6.
MAIN: MOV TMOD,#12H
T0ISR: CPL P1.7
T1ISR: CLR TR1
- There is no need for a “CLR TFx” instruction in timer ISR.
- 8051 clears the TF internally upon jumping to ISR.
- We must reload timer in mode 1.
- There is no need on mode 2 (timer auto reload)
Interrupt PrioritiesWhat if two interrupt sources interrupt at the same time?
- The interrupt with the highest PRIORITY gets serviced first.
- All interrupts have a power on default priority order.
External interrupt 0 (INT0)
Timer interrupt0 (TF0)
External interrupt 1 (INT1)
Timer interrupt1 (TF1)
Serial communication (RI+TI)
- Priority can also be set to “high” or “low” by IP reg.
Interrupt Priorities (IP) Register
|Bit Designation||Bit Number||Function|
|PT2||IP.5||timer 2 interrupt priority bit (8052 only)|
|PS||IP.4||serial port interrupt priority bit|
|PT1||IP.3||timer 1 interrupt priority bit|
|PX1||IP.2||external interrupt 1 priority bit|
|PT0||IP.1||timer 0 interrupt priority bit|
|PX0||IP.0||external interrupt 0 priority bit|
- Notes by Prof. Sujit Wagh, SKNCOE, Pune
- WikiNote Foundation