Pad Design

The circuitry on a chip has to connect with other circuits. These may be chips or display devices, transducers or electro-mechanical devices and the capacitance connected to the chip could be very large. In some cases the devices being driven will require or supply TTL signal levels, in others they may be liable to be short circuits, have high noise levels or be liable to discharge spikes of several kV. Each of these situations will require the imposition of circuitry to interface the chip to the external environment. Most IC designers avoid the problem of pad design and take pad drivers from standard libraries.

Physically, pads are the squares of metal, generally 100-150  m square, that are connected to the pins of the package with bonding wires. The word pad is often used to also include the circuitry that is used to interface the CMOS logic within the IC (typically composed of near minimum-geometry transistors) to the outside world. At least two pads in each circuit will be used to connect the chip to the VDD and VSS power supply lines, while other pads will be used for input connections and output connections. Some pads may also be required to be bi-directional, (for use both with input signals and output signals). In such cases there is usually a control connection to determine the direction of signal transfer.

An important function for all pad driver circuitry is the protection of the chip circuitry against destruction due to overvoltage pulses or sustained overvoltages. These may be due to electrostatic discharges or due to faults on other circuitry that cause unexpectedly high voltages to be applied to the chip pins.

Although it is possible to introduce overvoltages onto the chip via the supply connections, it is not feasible to provide any form of protection on these lines. They are, in any case, less sensitive to overvoltage than the signal connection.

The important considerations for the supply connections are the current requirements of the chip. There is an advantage in using multiple power supply pads, if the area is available, because this reduces noise levels. The 150  m by 150  m area typically used for the pad itself is likely will be adequate for the chip power requirements, but power buses of this width would take up too great a chip area. The necessary bus width must be calculated from the power requirements of the chip circuitry to:-

  • Keep the voltage drops within acceptable limits;
  • Keep the current density below the level that causes electromigration in the aluminium (approximately 109 Am-2). This phenomenon can give rise to gaps in power buses unless the current density is kept below about 1mA/m m width.

Input Pads

Input pads always contain overvoltage protection features, but can also contain inverting circuitry or Schmitt trigger circuitry if the input signals to be fed to the circuit are not known to be proper CMOS level signals.

An unprotected CMOS transistor typically has an input impedance greater than 1014  . The capacitance of the gate is also very small, so sufficient electrostatic charge can easily be accumulated to produce a voltage high enough to cause failure of the input transistor. With modern processes, a voltage of only about 30 V or so is required to break down the thin gate oxide, although experiments have shown that failure is often caused by non-uniform current flow producing current densities that give thermal breakdown first. The action of walking across a synthetic carpet can give an individual a potential of 15 kV, so the first precaution is obviously to try to prevent electrostatic charge coming into contact with the chip pins. It is normally recommended that electrostatic kits with earthed mats and wrist straps are used for handling CMOS devices, but this is still not an adequate safeguard because so little charge is required.

The usual protection circuit consists of a resistance and diode clamps, as shown in Figure below.

Input-Protection-Circuit

Figure  Input protection circuit 

D1 will turn on if the voltage at X rises significantly above VDD; similarly, D2 clamps the potential close to VSS if X is driven negative. The resistor R is normally a polysilicon track of about 1K and this is used to limit the maximum current that can flow through the diodes (in the event of the diode turning on) to a non-destructive level. Modern designs tend to make use of a diffused resistor (for example, p-type diffusion in an n-well) even though this carries with it the risk of inducing latchup as a result of the injection of extra charge into the substrate under extreme conditions, e.g. voltage overshoot transients. As an alternative, a polysilicon resistor may be used (although it occupies more space); the thick field oxide isolation guards against the possibility of charge injection. An example of input pad layout is shown in Figure below

Input-PAD-with-Polysilicon-Resistor

Figure  Input pad with a polysilicon resistor

The presence of the diodes reduces the input resistance of the circuit to ~1010 ohms. This is not likely to be important, but the effect of the protection structure on the speed of the circuit may be significant. The 1 k resistor and the input capacitance of the first stage of the circuit will present an RC time-constant. If this time constant is unacceptable the value of the resistor can be reduced, but this will reduce the voltage capability of the protection circuit. Protection circuits should have a capability of about 2kV and 8 kV capability is possible with careful design without unreasonable degradation of the speed of the circuit.

Drivers for Output Pads

Output pads must be capable of providing relatively large currents for off-chip wiring, perhaps the inputs to several other devices. This must all be done with minimum expenditure of area and without slowing down signals to an unacceptable extent. In general, the faster a circuit is required to run, the higher the output current drive capability must be because charge must be delivered more rapidly to the device being driven. The driver circuit must act as a buffer so that changes in output loading do not affect the rest of the chip circuitry. Drivers are typically composed of logic inverters with high current drive capability. Often an even number of inverters may be connected in cascade if a non-inverting driver structure is required.

A Simple Pad Driver

The simplest type of design just uses a single inverter, but with very large transistors that have a high current-drive capability. A design of this type is shown in Figure 

A Simple PAD driver

Figure A simple pad driver

The most notable features of this circuit are the numerous contacts to the well and the substrate and the unusual geometric arrangement of the transistors. The problems of latchup are greatest at I/O structures because the transistors used are large and the currents flowing are high. As a result, it is mandatory to use as many substrate and well contacts as possible, the normal guideline of ‘one per inverter’ being over-ridden here.

The geometric arrangement tries to ensure that the source fingers are perpendicular to the dominant direction of current flow. This is again a device to try to reduce the likelihood of latchup. There is also a relatively large spacing between the n and p transistors, which will also reduce the likelihood of latchup. Because the currents carried are large, a number of vias are used for the contacts between the two metal layers.

The sizing of the transistors depends on the capacitance of the load being driven and the required rise and fall times, T R and T F, for the output pulse. The relevant equations are:

T R =Rising-Time.png

T F=Falling_Time.png

where C is the load capacitance, VDD is the power supply potential, and W and L represent the width and length respectively of the n- and p-type pad driver transistor channels.

References

  • Notes by Prof.H.Dhanwate, ICOER, Pune
  • WikiNote Foundation
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Created by Sujit Wagh on 2017/08/07 17:30
Translated into en by Sujit Wagh on 2017/08/07 17:50