Interconnect Routing Techniques in VLSI

Updated on 2017/08/08 00:54

Interconnect Routing Techniques in VLSI Design

INTRODUCTION TO ROUTING
IN VLSI DESIGN

The routing is to locate a set of wires in the routing space that connect all the nets in the net list. The capacities of channels, width of wires, and wire crossings often need to be taken into consideration

THE ROUTING PROBLEM

—Apply after placement

—Input:

—Netlist

—Timing budget for, typically, critical nets

—Locations of blocks and locations of pins

—Output:

—Geometric layouts of all nets

—Objective:

—Minimize the total wire length, the number of vias, or just completing all connections without increasing the chip area.

Each net meets its timing budget

GENERAL ROUTING PROBLEM

 Two phases:

Global-and-Detailed-Routing

REGION DEFINITION 

Divide the routing area into routing regions of simple shape (rectangular):

Routing-Regions.png

•Channel: Pins on 2 opposite sides.

•2-D Switchbox: Pins on 4 sides.

•3-D Switchbox: Pins on all 6 sides.

ROUTING REGIONS IN DIFFERENT DESIGN STYLES

Gate-Array-Roting-Region-Design-Styles.png

TYPES OF ROUTING

routing-types.png

References

  • WikiNote Foundation
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Created by Sujit Wagh on 2017/08/08 00:38
Translated into en by Sujit Wagh on 2017/08/08 00:54