Clock-skew, Clock distribution techniques & jitter

Last modified by Vishal E on 2019/01/11 09:07

Clock-skew, Clock distribution techniques & jitter

Clock skew

Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit or source or clock definition point) arrives at different components at different times.due to

  • wire-interconnect length
  • temperature variations
  • capacitive coupling
  • material imperfections and
  • differences in input capacitance on the clock inputs

these factor became more critical for high frequency


Clock skew = (Arrival time at capture clock pin) - (Arrival time at launch clock pin)

Positive clock skew: If the clock arrival time at capture flip-flop is greater than that at launch flip-flop, clock skew is said to be positive.
Negative clock skew: Contrary to positive clock skew, if the clock arrival time at capture flip-flop is less than the launch flip-flop, clock skew is said to be negative.

Clock Jiiter

  • Jitter is the deviation from true periodicity of a presumably periodic signal, often in relation to a reference clock signal. In clock recovery applications it is called timing jitter.[1] Jitter is a significant, and usually undesired, factor in the design of almost all communications links.
  • Jitter can be quantified in the same terms as all time-varying signals, e.g., root mean square (RMS), or peak-to-peak displacement. Also like other time-varying signals, jitter can be expressed in terms of spectral density.
  • Jitter period is the interval between two times of maximum effect (or minimum effect) of a signal characteristic that varies regularly with time. Jitter frequency, the more commonly quoted figure, is its inverse. ITU-T G.810 classifies jitter frequencies below 10 Hz as wander and frequencies at or above 10 Hz as jitter.
  • Jitter may be caused by electromagnetic interference and crosstalk with carriers of other signals. Jitter can cause a display monitor to flicker, affect the performance of processors in personal computers, introduce clicks or other undesired effects in audio signals, and cause loss of transmitted data between network devices. The amount of tolerable jitter depends on the affected application.

Fig: Clock Jitter

Supply and Ground Bounce

Ground bounce is usually seen on high density VLSI where insufficient precautions have been taken to supply a logic gate with a sufficiently low resistance connection (or sufficiently high capacitance) to ground. In this phenomenon, when the gate is turned on, enough current flows through the emitter-collector circuit that the silicon in the immediate vicinity of the emitter is pulled high, sometimes by several volts, thus raising the local ground, as perceived by the transistor, to a value significantly above true ground. Relative to this local ground, the base voltage can go negative, thus shutting off the transistor. As the excess local charge dissipates, the transistor turns back on, possibly causing a repeat of the phenomenon, sometimes up to a half-dozen bounces.

Ground bounce is one of the leading causes of "hung" or metastable gates in modern digital circuit design. This happens because the ground bounce puts the input of a flip flop effectively at voltage level that is neither a one nor a zero at clock time, or causes untoward effects in the clock itself. A similar phenomenon may be seen on the collector side, called VCC sag, where VCC is pulled unnaturally low. As a whole, ground bounce is a major issue in nanometer range technologies in VLSI.

Ground bounce can also occur when the circuit board has poorly designed ground paths. Improper ground or VCC can lead to local variations in the ground level between various components. This most commonly seen in circuit boards that have ground and VCC paths on the surfaces of the board.

Ground-BalanceFig: Gound Bounce


  • Notes by Prof.H.Dhanwate, ICOER, Pune
  • WikiNote Foundation
Created by Vishal E on 2019/01/11 09:07