# VHDL Code for Combinational circuits

Updated on 2017/07/29 17:04

## Logical Operators in VHDL

 Logical Operation Operator Example AND AND $Z< =$ (A AND B); NAND NAND $Z< =$ (A NAND B); NOR NOR $Z< =$ (A NOR B); NOT NOT $Z< =$ (A NOT B); OR OR $Z< =$ (A OR B); XNOR XNOR $Z< =$ (A XNOR B); XOR XOR $Z< =$ (A X-OR B);

## Arithmetic Operators

 Arithmetic Operation Operator Example Addition + $Z< =$ (A + B) Substraction - $Z< =$ (A - B) Multiplication * $Z< =$ (A * B) Division / $Z< =$ (A / B) Exponentiating ** $Z< =$ 4**2 Modulus MOD $Z< =$ (A MOD B) Remainder REM $Z< =$ (A REM B) Absolute Value ABS $Z< =$ ABS A

## Relational Operators

 Relational Operation Operator Example Equal to $=$ $Z< =$ (A AND B); Not Equal to $/=$ $Z< =$ (A NAND B); Less Than $<$ $Z< =$ (A NOR B); Less Than or equal to $< =$ $Z< =$ (A NOT B); Greater than $>$ $Z< =$ (A OR B); Greater than or equal to $> =$ $Z< =$ (A XNOR B);

## VHDL codes for Combinational Circuits

### XOR GATE

library ieee;
use ieee.std_logic_1164.all;
--
entity xorGate is
port( A1, A2: in std_logic;
X1: out std_logic);
end xorGate;
--
architecture func of xorGate is
begin
X1<= A1 xor A2;
end func;

llibrary ieee;
use ieee.std_logic_1164.all;
--
port( A, B, Cin : in std_logic;
sum, Cout : out std_logic);
--Dataflow architecture.
begin
sum <= (A xor B) xor Cin;
Cout <= (A and (B or Cin)) or (Cin and Y);
end func;

### 4:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC
);
end multiplexer_4_1;

architecture multiplexer4_1_arc of multiplexer_4_1 is
begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(3);
elsif (sel="01") then
dout <= din(2);
elsif (sel="10") then
dout <= din(1);
else
dout <= din(0);
end if;
end process mux;
end multiplexer4_1_arc;

## References

• WikiNote Foundation
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Created by HrishikeshDhanawate on 2017/07/29 16:52

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