VHDL Code for Combinational circuits

Updated on 2017/07/29 17:04

 

Logical Operators in VHDL

Logical OperationOperatorExample
ANDANDZ< = (A AND B);
NANDNANDZ< = (A NAND B);
NORNORZ< = (A NOR B);
NOTNOTZ< = (A NOT B);
ORORZ< = (A OR B);
XNORXNORZ< = (A XNOR B);
XORXORZ< = (A X-OR B);

Arithmetic Operators

Arithmetic OperationOperatorExample
Addition+Z< = (A + B)
Substraction-Z< = (A - B)
Multiplication*Z< = (A * B)
Division/Z< = (A / B)
Exponentiating**Z< = 4**2
ModulusMODZ< = (A MOD B)
RemainderREMZ< = (A REM B)
Absolute ValueABSZ< = ABS A

Relational Operators

Relational OperationOperatorExample
Equal to=Z< = (A AND B);
Not Equal to/=Z< = (A NAND B);
Less Than<Z< = (A NOR B);
Less Than or equal to< =Z< = (A NOT B);
Greater than>Z< = (A OR B);
Greater than or equal to> =Z< = (A XNOR B);

VHDL codes for Combinational Circuits

XOR GATE

XOR logic gate and truth table with VHDL code

library ieee;
use ieee.std_logic_1164.all;
--
entity xorGate is 
port( A1, A2: in std_logic;
X1: out std_logic);
end xorGate;
--
architecture func of xorGate is
begin
X1<= A1 xor A2;
end func;

FULL  ADDER

Image result for full adder image

llibrary ieee;
use ieee.std_logic_1164.all;
--
entity Full_Adder is
port( A, B, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;
--Dataflow architecture.
architecture func of Full_Adder is
begin
sum <= (A xor B) xor Cin;
Cout <= (A and (B or Cin)) or (Cin and Y);
end func;

4:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC
);
end multiplexer_4_1;

architecture multiplexer4_1_arc of multiplexer_4_1 is
begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(3);
elsif (sel="01") then
dout <= din(2);
elsif (sel="10") then
dout <= din(1);
else
dout <= din(0);
end if;
end process mux;
end multiplexer4_1_arc;

 

References

  • WikiNote Foundation
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Created by HrishikeshDhanawate on 2017/07/29 16:52