Syllabus

  • VHDL Modeling: Meta-stability

Metastability

What is Meta-stability

In general metastability is an un-avoidable behavior of circuit that may cause malfunction or circuit "this means that the signal can come from another uncorrelated clock clocked circuit", 
From a specification point of view, synchronous elements such as flip flops specify a Setup time and a Hold time. By its nature an asynchronous input cannot be reliably expected to meet this specification, and so it will have transitions that fall within the timing window that is bounded by these two specifications.

When this occurs, the result can be one of three scenarios:

  1. The state of the signal prior to the transition is used,
  2. the state of the signal after the transition is used or
  3. the flip flop goes metastable.

The third possibility is what matters here because in the two other situation the element will stay in it state or go to another state which is irrelevant to an asynchronous signal behavior.
So actaully asynchronous signal transition may violates the steup and hold time of the flipflop, however metastability actually occurs within a tiny timing window, when the input does not violate the setup and hold timing specifications only but also when the flipflop accepts the new input, this causes an unstable equilibrium state under this symmertrically balanced transitory state is called the metastability. 

In fact the device may stop acting like a digital one and may act as an analog device, this also may cause a propagation of this situation to other cascaded elements in the circuit "you got a series of amplifiers for example", this may cause circuit failure or malfunction "not often to happen with CMOS".

Example: In digital logic all your circuits should be either be in logic 1 or logic 0 . lets consider that 3.3v represents logic 1 and 0v represents logic 0. so the circuit should be in one of the 2 voltage levels. Meta stablity is a condition where the voltage level is in between these 2 voltge levels.
This does not represent a logic 0 or logic 1 and drives your digital circuit crazy. 

How is this caused

  1. Using asynchronus resets -> consider the condition where reset is released exactly at the positive edge of your clock. Should the Flipflop stay in reset state or capture what is in the data-in pin , usally what happens is that it goes to metastablilty.
  2. When transfering data from one clock domain to another clock domain -> what if the data -in pin changed exactly at the positive edge of your clock, again metastabilty !

How to avoid Meta-stability

Care to be taken

  1. Use synchronus resets ( or atleast sychronize the reset release mechanism)
  2. When transfering data across different clock domain use synchornizing flops

References

  • Created and Edited by Prof H.Dhanwate, JSPM's ICOER, Pune
  • WikiNote Foundation
Tags:
Created by HrishikeshDhanawate on 2017/07/28 21:24