Entity, Architecture and Types of Modeling

Updated on 2017/07/29 17:00

Syllabus

  • VHDL Modeling: Entity, Architecture & types of modeling

Entity

  • Entity is the description of the interface between a design and its external environment.
  • It may also specify the declarations and statements that are part of the design entity.
  • A given entity declaration may be shared by many design entities, each of which has a different architecture.
  • Thus, an entity declaration can potentially represent a class of design entities, each having the same interface.

Simplified Syntax

entity entity_name is
generic (generic_list);
port (port_list);]
end entity entity_name;

Example 1

library IEEE;
use IEEE.std_logic_1164.all;
entity BCD_Decoder is
port (
BCD : in Bit_Vector (2 downto 0);
Enable : in Bit;
LED : out Std_Ulogic_Vector (3 downto 0));
constant ZERO : Std_Ulogic_Vector(3 downto 0) := "0000";
begin
assert (BCD /= "111") report "BCD = 7 " severity note;
end entity BCD_Decoder;
entity and_or is
port(
a : in std_logic;
b : in std_logic;
d : in std_logic;
e : in std_logic;
g : out std_logic);
end and_or;
architecture and_or_a of and_or is
component and2 -- and2 component declaration
port(
a : in std_logic;
b : in std_logic;
c : out std_logic);
end component;
component or2 -- or2 component declaration
port(
a : in std_logic;
b : in std_logic;
c : out std_logic);
end component;
signal c : std_logic; -- wire used to connect
signal f : std_logic; -- the component
begin
-- and2 component instance
u1: and2
port map(
a => a,
b => b,
c => c);
-- and2 component instance
u2: and2
port map(
a => d,
b => e,
c => f);
-- or2 component instance
u3: or2
port map(
a => c,
b => f,
c => g);
end and_or_a;

Architecture

  • The entity/architecture combination is the most fundamental building block in VHDL.
  • Entities and Architectures are used together to define a piece of functionality.
  • There should only be one entity and architecture for each file.
  • Often a large FPGA design is broken into many entity/architect combinations.
  • The entity contains the port map. The port map is used to define all input and output signals for a particular entity.
  • Signals can be one of three types: in, out, and inout. In and Out are self-explanatory, inout is a bidirectional signal that can be either an input or an output.
  • In general, inouts should not be used until you gain some confidence in your FPGA designs, as they are more involved.

978401850.png

VHDL code for Nand Gate

library ieee;
use ieee.std_logic_1164.all;
entity example_entity_architecture is
port (
i_bit_1 : in std_logic;
i_bit_2 : in std_logic;
o_bit: out std_logic
);
end example_entity_architecture;
architecture behave of example_entity_architecture is
begin
p_PROCESS: process (i_bit_1, i_bit_2)
begin
o_bit <= i_bit_1 and i_bit_2;
end process p_PROCESS;
end behave;

Types of Modelling

Data Flow Modeling

In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.

Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct code.

Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.

In concurrent code, the following can be used:

  • Operators
  • The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
  • The GENERATE statement;
  • The BLOCK statement

Behavioral Modeling

In this modeling style, the behavior of an entity as set of statements is executed sequentially in the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential.

PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially.

However, as a whole, any of these blocks is still concurrent with any other statements placed outside it.

One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it, we can build sequential circuits as well as combinational circuits.

The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and they are supposed to be used in sequential code only. VARIABLE can never be global, so its value cannot be passed out directly.

Structural Modeling

In this modeling, an entity is described as a set of interconnected components. A component instantiation statement is a concurrent statement. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components (viewed as black boxes), without implying any behavior of the components themselves nor of the entity that they collectively represent.

In Structural modeling, architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin).

NAND Gate with Truth table and VHDL

Examples

NAND GATE using behavioral Modeling Style

library ieee;
use ieee.std_logic_1164.all;
------------------------------------------
entity NAND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NAND_ent;

------------------------------------------
architecture behv1 of NAND_ent is
begin
process(x, y)
begin

-- compare to truth table
if (x='1' and y='1') then
F <= '0';
else
F <= '1';
end if;
end process;
end behv1;

NAND GATE using Data Flow Modeling Style

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_gate is
Port ( A1 : in STD_LOGIC; -- NAND gate input 1
A2 : in STD_LOGIC; -- NAND gate input 2
X1 : out STD_LOGIC; -- NAND gate output
end nand_gate_top;
architecture Behavioral of nand_gate is
begin
X1 <= A1 nand A2; -- 2 input NAND gate
end Behavioral;

Half adder

A half adder is a logic circuit that performs one-digit addition.It has two inputs (the bits to be summed) and two outputs (the sum bit and the carry bit). An example of a Boolean half adder is this circuit in figure (1):

Half Adder
Figure : Half Adder

The Behavioral Model for the half adder :

library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port (a : in std_logic;
b : in std_logic;
sum : out std_logic;
cout : out std_logic);
end half_adder;
architecturebasic_beh of half_adder is
begin
process (a,b)
begin
if (a = '1' and b = '1') then
sum<= '0' ;
cout<= '1';
elsif (a = '1' and b = '0') then
sum<= '1' ;
cout<= '0';
elsif (a = '0' and b = '1' )then
sum<= '1' ;
cout<= '0';
elsif (a = '0' and b = '0') then
sum<= '0' ;
cout<= '0';
else
sum<= '0' ;
cout<= '0';
end if;
end process;
endbasic_beh;

The Data flow Model for the half adder :

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(a,b:in bit;
sum,carry:out bit);
end half_adder;
architecture data of half_adder is
begin
sum<= a xor b;
carry <= a and b;
end data;

The Structural Model for the half adder :

architecturebasic_struct of half_adder is

begin
and1: entity work.and2(basic_and)
port map (a,b,cout);
xor1: entity work.XOR2(basic_XOR)
port map (a,b,sum);
endbasic_struct;
library IEEE;
use IEEE.std_logic_1164.all;
entityand2 is
port (x : in std_logic;
y : in std_logic;
z: out std_logic);
endand2;

architecturebasic_and of and2 is

begin
z<= x and y;
endbasic_and;
library IEEE;
use IEEE.std_logic_1164.all;
entityXOR2 is
port (x : in std_logic;
y : in std_logic;
z: out std_logic);
endXOR2;

architecturebasic_XOR of XOR2 is

begin
z<= x and y;
endbasic_XOR;

References

  • Edited and Created by Prof Hrishikesh Dhanwate, JSPM'S ICOER,Wagholi ,Pune
  • WikiNote Foundation
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Created by HrishikeshDhanawate on 2017/07/29 16:30