Concurrent Statements

Updated on 2017/07/29 17:01

Syllabus

  • VHDL Modeling: Concurrent statements

VHDL Concurrent Statements

These statements are for use in Architectures. Following are the types of concurrent statements list:

  1. block statement
  2. process statement
  3. concurrent procedure call statement
  4. concurrent assertion statement
  5. concurrent signal assignment statement
  6. conditional signal assignment statement
  7. selected signal assignment statement
  8. component instantiation statement
  9. generate statement

Block statement

Used to group concurrent statements, possibly hierarchically.  

label : block [ ( guard expression ) ] [ is ]
[ generic clause [ generic map aspect ; ] ]
[ port clause [ port map aspect ; ] ]
[ block declarative items ]
begin
concurrent statements
end block [ label ] ;
clump : block
begin
A <= B or C;
D <= B and not C
end block clump ;
maybe : block ( B'stable(5 ns) ) is
port (A, B, C : inout std_logic );
port map ( A => S1, B => S2, C => outp );
constant delay: time := 2 ns;
signal temp: std_logic;
begin
temp <= A xor B after delay;
C <= temp nor B;
end block maybe;

Process statement

Used to do have sequential statements be a part of concurrent processing.

label : process [ ( sensitivity_list ) ] [ is ]
[ process_declarative_items ]
begin
sequential statement
end process [ label ] ;
-- input and output are defined a type 'word' signals
reg_32: process(clk, clear)
begin
if clear='1' then
output <= (others=>'0');
elsif clk='1' then
output <= input after 250 ps;
end if;
end process reg_32;
-- assumes  use IEEE.std_logic_textio.all
printout:process(clk) -- used to show state when clock raises
variable my_line : LINE;-- not part of working circuit
begin
if clk='1' then
write(my_line, string'("at clock "));
write(my_line, counter);
write(my_line, string'("  PC="));
write(my_line, IF_PC);
writeline(output, my_line);
counter <= counter+1;
end if;
end process printout;

Process_declarative_items are any of:

  • subprogram declaration
  • subprogram body
  • type declaration
  • subtype declaration
  • constant, object declaration
  • variable, object declaration
  • file, object declaration
  • alias declaration
  • attribute declaration
  • attribute specification
  • use clause
  • group template declaration
  • group declaration

BUT NOT signal_declaration, all signals must be declared outside the process.
    sig1 <= sig2 and sig3; -- considered here as a sequential statement
                          -- sig1 is set outside the process upon exit or wait

A process may be designated as postponed in which case it starts in thesame simulation cycle as an equivalent non postponed process, yet starts after all other non postponed processes have suspended in that simulation cycle.

Concurrent procedure call statement

A sequential procedure call statement may be used and its behavior is that of an equivalent process. 

[ label : ] [ postponed ] procedure name [ ( actual_parameters ) ] ;
trigger_some_event ;
Check_Timing(min_time, max_time, clk, sig_to_test);

Note that a procedure can be defined in a library package and then used many places.  A process can not be similarly defined in a package and may have to be physically copied.  A process has some additional capability not available in a concurrent procedure.

Concurrent assertion statement

A sequential assertion statement may be used and its behavior is that of an equivalent process.

[ label : ] [ postponed ] assertion_statement ;

Concurrent signal assignment statement

A sequential signal assignment statement is also a concurrent signal assignment statement. Additional control is provided by the use of postponed and guarded.

[ label : ] sequential signal assignment statement
[ label : ] [ postponed ] conditional_signal_assignment_statement ;
[ label : ] [ postponed ] selected_signal_assignment_statement ;

The optional guarded causes the statement to be executed when the guarded signal changes from False to True.

Conditional signal assignment statement

A conditional assignment statement is also a concurrent signal assignment statement.

target <= waveform when choice; -- choice is a boolean expression
target <= waveform when choice else waveform;
sig <= a_sig when count>7;
sig2 <= not a_sig after 1 ns when ctl='1' else b_sig;

"waveform" for this statement seems to include [ delay_mechanism ] See sequential signal assignment statement

Selected signal assignment statement

A selected assignment statement is also a concurrent signal assignment statement. 

with expression select target <=
waveform when choice [, waveform when choice ] ;
with count/2 select my_ctrl <=
'1' when 1, -- count/2 = 1 for this choice
'0' when 2,
'X' when others;

Component instantiation statement

Get a specific architecture-entity instantiated component. 

part_name: entity
library_name.entity_name(architecture_name)
port map ( actual arguments ) ;
optional (architecture_name)
part_name: component_name
port map ( actual arguments ) ;

Given entity gate is

port (in1 : in std_logic ;
in2 : in std_logic ;
out1 : out std_logic) ;
end entity gate;
architecture circuit of gate is ...
architecture behavior of gate is ...
A101: entity WORK.gate(circuit)
port map ( in1 => a, in2 => b, out1 => c );
--when gate has only one architecture
A102: entity WORK.gate
port map ( in1 => a, in2 => b, out1 => c );
-- when order of actual arguments is used
A103: entity WORK.gate
port map ( a, b, c );

Given an entity

entity add_32 is -- could have several architectures
port (a : in std_logic_vector (31 downto 0);
b : in std_logic_vector (31 downto 0);
cin : in std_logic;
sum : out std_logic_vector (31 downto 0);
cout : out std_logic);
end entity add_32;

Create a simple component interface

component add_32 -- use same port as entity
port (a: in std_logic_vector (31 downto 0);
b : in std_logic_vector (31 downto 0);
cin : in std_logic;
sum : out std_logic_vector (31 downto 0);
cout : out std_logic);
end component add_32;

Instantiate the component 'add_32' to part name 'PC_incr'

PC_incr : add_32 port map (PC, four, zero, PC_next, nc1);

Create a component interface, changing name and renaming arguments

component adder-- can have any name but same types in port
port (in1 : in std_logic_vector (31 downto 0);
in2 : in std_logic_vector (31 downto 0);
cin : in std_logic;
sum : out std_logic_vector (31 downto 0);
cout : out std_logic);
end component adder;

Instantiate the component 'adder' to part name 'PC_incr'

PC_incr : adder-- configuration may associate a specific architecture
port map (in1 => PC,
in2 => four,
cin => zero,
sum => PC_next,
cout => nc1);

Generate statement

Make copies of concurrent statements

label: for variable in range generate-- label required
block declarative items---optional 
begin
concurrent statements--- using variable
end generate label ;
label: if condition generate-- label required
block declarative items----optional
begin
concurrent statements
end generate label ;
band : for I in 1 to 10 generate
b2 :for J in 1 to 11 generate
b3 :if abs(I-J)<2 generate
part: foo port map ( a(I), b(2*J-1), c(I, J) );
end generate b3;
end generate b2;
end generate band;

References

  • Edited and Created by Prof. Hrishikesh Dhanwate, JSPM's ICOER, Wagholi, Pune
  • WikiNote Foundation
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Created by HrishikeshDhanawate on 2017/07/28 23:14