Aug-2017 In-SEM Exam Model Answer Paper

Updated on 2017/08/11 15:56

Model Answer Paper for VLSI Design and Technology

Note: Model answers and marking scheme is totally based on my knowledge and experience. This model answer is not provided by SPPU. There may be changes in marking scheme of SPPU Exam panel.

Question 1

a) Write VHDL code for 2:1 mux in structural as well as behavioural modelling styles. (5 Marks)

VHDL code using structural modelling style 

2 and 1/2 Marks

WikiNote: 

 

VHDL code using Behavioural modelling style 2 and 1/2 Marks

b)What is meant by metastability?Explain any one solution in detail.  (5 Marks)

Metastability defination2 MarksWikiNote: Metastability
For any one solution.3 MarkWikiNote: Solution

OR

Question 2

a) What is subprogram?Explore with suitable VHDL code. (5 Marks)

subprogram defination2 MarksWikiNote: Subprogram
For VHDL code.3 MarksWikiNote: 

b)  What is need of attributes? Explain any three attributes in brief. (5 Marks)

Explaination of Need of attributes

2 Marks
Attribute Explaination (Any three attributes)3 Marks

Question 3

a) With the  help of suitable diagram of architectural details.explain the typical specifications of FPGA.(5 Marks)

Architectural diagram2 MarksWikiNote: Diagram
for any three specification3 MarksWikiNote: Specifications

b) Compare CPLD & FPGA architectural in brief (5 Marks)

For each point(1 marks)5 MarksWikiNote:

OR

Question 4

a) What is meant by synthesis in design flow? Explain in detail (5 Marks)

Defination of Synthesis design flow.1 MarksWikiNote: 
For Detail explaination.4 Mark

WikiNote: 

b) Explore different types of simulation involved in high level design flow.Explore post layout simulation in detail.  (5 Marks)

For each type of simulation(1 mark)3 MarksWikiNote: 
For explaination of post layout simulation2 MarksWikiNote: 

Question 5

a) Explain signal integrity issues involved in VLSI design. (5 Marks)

Each point (1 mark)5 Marks WikiNote: Signal integrity issues

b) Write note on pad design (5 Marks)

For detail explaination.5 MarksWikiNote: PAD Design

OR

Question 6

a) What is the reason of clock skew? List various clock distribution techniques. Explain any one of them  (5 Marks)

For defination of clock skew1 Marks WikiNote: Definition
For different types of techniques.2 Marks WikiNote: Techniques
For explanation of any one2 MarksWikiNote:

b) Writes note on architectures for low power (5 Marks)

Explanation in detail. 6 points5 MarksWikiNote: Architecture for low power

References

  • Marking scheme Prepared by Prof. Saurabh S.Padmawar, SKNCOE, Pune
  •  Answer by Prof.H.Dhanwate, ICOER, Wagholi ,Pune
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Created by Sujit Wagh on 2017/08/08 14:38