MSSP (SPI-I2C) module in PIC18Fxxx

Updated on 2017/11/16 23:59

 

Master Synchoronus Serial Port(MSSP) Module

The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
The MSSP module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call)
The I2C interface supports the following modes in hardware:
• Master mode
• Multi-Master mode
• Slave mode

Control Registers

The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. 

MSSP-SPI-mode

The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation:
• Slave Select (SS) – RA5/SS Figure shows the block diagram of the MSSP module when operating in SPI mode

MSSP-SPI-Mode-Operation.png

REGISTERS

The MSSP module has four registers for SPI mode operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation.
The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. 

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

76543210
SMPCKED/APSR/WUABF
BitDescription
7 SMP: Sample bit SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. 
6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state 
5 D/A: Data/Address bit Used in I2C™ mode only. 
4 P: Stop bit Used in I2C mode only.
This bit is cleared when the MSSP module is disabled, SSPEN is cleared. 
3 S: Start bit Used in I2C mode only. 
2 R/W: Read/Write Information bit Used in I2C mode only. 
1 UA: Update Address bit Used in I2C mode only. 
0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty 

SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)

76543210
WCOLSSPOVSSPENCKPSSPM3SSPM2SSPM1SSPM0
BitDescription
7WCOL: Write Collision Detect bit
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow 
5 SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins 
4CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin; SS pin control disabled; SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin; SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 

OPERATION

When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified:

  • Master mode (SCK is the clock output)
  • Slave mode (SCK is the clock input)
  • Clock Polarity (Idle state of SCK)
  • Data Input Sample Phase (middle or end of data output time) 
  • Clock Edge (output data on rising/falling edge of SCK)
  • Clock Rate (Master mode only)
  • Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. 

MSSP-I2C-mode

Block-Diagram

MSSP-I2C-Mode(Slave)-Operation.png

FIG: MSSP BLOCK DIAGRAM (I2C MODE)    

The MSSP module in I2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-Bit and 10-Bit Addressing modes.

Pin Description

Signal

Pin No.

Symbol

SCL (Serial Clock)

34

RB1/AN10/INT1/SCK/SCL

SDA (Serial Data)

33

RBO/AN12/INTO/FLTO/SDI/SDA

Note-The user must configure these pins as inputs by setting the associated TRIS bits.

MSSP( I2C Mode) REGISTERS

The MSSP module has six registers for I2C operation. These are: I2C Register Map:

SFR

Description

Access

Reset Value

Address

SSPCON1

MSSP Control Register 1

Read/Write

Ox00

OxFC6

SSPCON2

MSSP Control Register 2

Read/Write

Ox00

OxFC5

SSPSTAT

MSSP Status Register

Read

Ox00

OxFC7

SSPADD

MSSP Address Register

Write

Ox00

OxFC8

SSPBUF

Serial Rx/Tx Buffer Register

Read/Write

unknown

OxFC9

SSPSRMSSP Shift RegisterNot Accesible--

Operation

  • SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.
  • SSPSR is the shift register used for shifting data in or out.
  • SSPBUF is the buffer register to which data bytes are written to or read from.
  • SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode.
  • When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value.
  • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver.
  • When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
  • During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR. 

SSPCON1: MSSP CONTROL REGISTER 1 (I2C Mode)

76543210
WCOLSSPOVSSPENCKPSSPM3SSPM2SSPM1SSPM0

Register Description

Bit No.

Control Bit

Description

Bit 7

WCOL

Write Collision Bit

Bit 6

SSPOV

Receive Overflow Indicator bit

Bit 5

SSPEN

Master Synchronous Serial Port Enable bit

1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/0 pins

Bit 4

CKP

SCK Release Control bit

Bit 3-0

SSPM3:SSPMO

Master Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address vyrith Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1000 = 12C Master mode, clock=FOSC/(4 *(SSPADD+1)) 0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address

MSSP Control Register 2 (SSPCON2); MASTER MODE

76543210
GCENACKSTATACKDTACKENRCENPENRSENSEN

Register Description 

Bit No.

Control Bit

Description

Bit 7

GCEN

General Call Enable bit (Slave mode only)

Bit 6

ACKSTAT

Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave

Bit 5

ACKDT

Acknowledge Data bit (Master Receive mode only)

Bit 4

ACKEN

Acknowledge Sequence Enable bit

Bit 3

RCEN

Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle

Bit 2

PEN

Stop Condition Enable bit
1 = Initiate Stop condition. Automatically cleared by H/W
0 = Stop condition Idle

Bit 1

RSEN

Repeated Start Condition Enable bit
1 = Initiate Repeated Start condition. Automatically cleared by hardware.
0 = Repeated Start condition Idle

Bit 0

SEN

Start Condition Enable/Stretch Enable bit

1 = Initiate Start condition. Automatically cleared by hardware.
0 = Start condition Idle

SSPSTAT: MSSP STATUS REGISTER (I2C MODE)

76543210
SMPCKED/APSR/WUABF

Register Description 

Bit No.

Control Bit

Description

Bit 7

SMP

Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)

Bit 6

CKE

SMBus Select bit

Bit 5

D/A

Data/Address bit

Bit 4

P

Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last

Bit 3

5

Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last

Bit 2

R/W

Read/Write Information bit

In Slave mode: 1 = Read
0 = Write

In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress

Bit 1

UA

Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

Bit 0

BF

Buffer Full Status bit

In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty

In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop)

SSPADD Register

SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value

76543210
-Baud Rate Generator Reload Value

For Exapmple:-

I2C Master mode

SSPM3: SSPMO = 1000 (SSPCON1)

I2C Clock = Fosc/(4 +(SSPADD+1))

Case 1: For Fosc = 48 Mhz and I2C Clock = 100Khz

SSPADD = ((Fosc/(4*I2C Clock)) - 1

SSPADD = ((48x107(4*100x10:)) - 1 SSPADD = (119)10 = (77)16

Case 2: For Fosc = 20 Mhz and I2C Clock = 100Khz

SSPADD = ((Fosc/(4*I2C Clock)) - 1

SSPADD = ((20x101/(4+100x10 )) - 1 SSPADD = (49)10 = (31)16

References

  • Created and Developed by Prof Sujit Wagh, Sinhgad's SKNCOE, Pune
  • WikiNote Foundation
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Created by Sujit Wagh on 2017/09/25 13:43