Capture/Compare/PWM (CCP) Module

Updated on 2017/09/25 10:14

Capture/Compare/PWM (CCP) Module

Capture Compare PWM Module

PIC18F2420/2520/4420/4520 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 40/ 44-pin devices, CCP1 is implemented as an Enhanced CCP module with standard Capture and Compare modes and Enhanced PWM modes.The capture and compare operations described in this chapter apply to all standard and Enhanced CCP modules. 

CCPxCON Register

5DCBx1 PWM mode: This bit is LSB  (bit 1) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL
4DCBx0 PWM mode: This bit is LSB  (bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL
3-0CCPx Module Mode Select bits
  • 0000 = Capture/Compare/PWM disabled (resets CCPx module)
  • 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set)
  • 0011 = Reserved 0100 = Capture mode, every falling edge
  • 0101 = Capture mode, every rising edge
  • 0110 = Capture mode, every 4th rising edge
  • 0111 = Capture mode, every 16th rising edge
  • 1000 = Compare mode, initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
  • 1001 = Compare mode, initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
  • 1010 = Compare mode, generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state)
  • 1011 = Compare mode, trigger special event; reset timer; CCP2 match starts A/D conversion (CCPxIF bit is set)
  • 11xx = PWM mode

CCP Module Configuration

  • Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 


CCP/ECCP ModeTimer Resource
CaptureTimer1 or Timer3
CompareTimer1 or Timer3

Capture Mode

In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the corresponding CCPx pin.
An event is defined as one of the following:

  • every falling edge
  • every rising edge
  • every 4th rising edge
  • every 16th rising edge

The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value is overwritten by the new captured value


In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit.       


The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation will not work. The timer to be used with each CCP module is selected in the T3CON register

Software Interrupt

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode


There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. 

Capture Mode Block Diagram


Compare Mode

In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value.
When a match occurs, the CCPx pin can be:

  • driven high
  • driven low
  • toggled (high-to-low or low-to-high)
  • remain unchanged (that is, reflects the state of the I/O latch)

The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. 


The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit.


Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.


When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is not affected. A CCP interrupt is generated when the CCPxIF interrupt flag is set while the CCPxIE bit is set.


Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM<3:0> = 1011). For either CCP module, the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module’s time base. This allows the CCPRx registers to serve as a programmable Period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D Converter must already be enabled.

Compare Mode Block Diagram


PWM Mode

In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output.Figure shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section “Setup for PWM Operation”.


PWM Output


PWM period

It is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: 

 PWM Period=[(PR2)+1]• 4 • TOSC • (TMR2 Prescale Value)

PWM frequency

 It is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle:

PWM frequency= 1/ [PWM period]

  • TMR2 is cleared
  • The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set)
  • The PWM duty cycle is latched from CCPRxL into CCPRxH   


The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available.
The CCPRxL contains the eight MSbs and the CCPxCON<5:4> bits contain the two LSbs.
This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. The following equation is used to calculate the PWM duty cycle in time

PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • TOSC • (TMR2 Prescale Value)

Set-Up for PWM Operation

CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register.
The following steps should be taken when configuring the CCP module for PWM operation:

  1. Set the PWM period by writing to the PR2 register.
  2. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits.
  3. Make the CCPx pin an output by clearing the appropriate TRIS bit.
  4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON.
  5. Configure the CCPx module for PWM operation.

Embedded C Program

Program:- Write an embedded C program to generate PWM waveform of 1Khz frequency with 25%,50%,75%,100% Duty cycle. Assume XTAL=4MHz and Prescaler=4.Observe the output on Digital oscilloscope

#pragma config OSC=HS
#pragma config PWRT=OFF
#pragma config WDT=OFF
#pragma config DEBUG=OFF, LVP=OFF
void DELAY();
void main()
TRISC=0x00;   ///RC2 pin as PWM output pin
PR2=250;      ////PR2=(Fosc/4xNxFpwm)
T2CON=0X01;  ///Prescaler=4
while(1)      ///forever loop
CCP1CON=0X2C;    ///PWM mode, DCB1:DCB0=0.50 Decimal points
CCPR1L=62;       //25% Duty cycle
CCP1CON=0X0C;///PWM mode, DCB1:DCB0=0.00 Decimal points
CCPR1L=125;       //50% Duty cycle
CCP1CON=0X2C;///PWM mode, DCB1:DCB0=0.50 Decimal points
CCPR1L=187;     //75% Duty cycle
CCP1CON=0X0C;///PWM mode, DCB1:DCB0=0.00 Decimal points
CCPR1L=250;           //100% Duty cycle
TMR2=0x00;               //load TMR2=00H
PIR1bits.TMR2IF=0;        //Clear interrupt flag
T2CONbits.TMR2ON=1;        //start timer 2
while(PIR1bits.TMR2IF==0);  ///monitor TMR2 interrupt flag

void DELAY()
unsigned int i,j;

Interfacing Diagram


Video Proteus Simulation


  • Created and Developed by Sujit wagh, SKNCOE
  • WikiNote Foundation
Created by Sujit Wagh on 2017/09/23 16:23
Translated into en by Sujit Wagh on 2017/09/23 17:13