Timers in PIC18Fxxx Microcontroller

Updated on 2017/11/17 15:05

Syllabus

  • PIC Microcontroller Architecture - timer and its programming

Timer0 Module

The Timer0 module incorporates the following features:

  • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes
  • Readable and writable registers
  • Dedicated 8-bit, software programmable prescaler
  • Selectable clock source (internal or external)
  • Edge select for external clock
  • Interrupt-on-overflow

The T0CON register controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure. Figure shows a simplified block diagram of the Timer0 module in 16-bit mode.

T0CON

76543210
TMR0ONT08BITT0CST0SEPSAT0PS2T0PS1T0PS0
BitDescription
7TMR0ON: Timer0 On/Off Control bit
  • 1 = Enables Timer0
  • 0 = Stops Timer0 
6T08BIT: Timer0 8-Bit/16-Bit Control bit
  • 1 = Timer0 is configured as an 8-bit timer/counter
  • 0 = Timer0 is configured as a 16-bit timer/counter 
5T0CS: Timer0 Clock Source Select bit
  • 1 = Transition on T0CKI pin
  • 0 = Internal instruction cycle clock (CLKO) 
4T0SE: Timer0 Source Edge Select bit
  • 1 = Increment on high-to-low transition on T0CKI pin
  • 0 = Increment on low-to-high transition on T0CKI pin 
3PSA: Timer0 Prescaler Assignment bit
  • 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
  • 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output
2R/W: Read/Write Information bit Used in I2C mode only. 
1-0T0PS<2:0>: Timer0 Prescaler Select bits
  • 111 = 1:256 Prescale value
  • 110 = 1:128 Prescale value
  • 101 = 1:64   Prescale value
  • 100 = 1:32   Prescale value
  • 011 = 1:16   Prescale value
  • 010 = 1:8     Prescale value
  • 001 = 1:4     Prescale value
  • 000 = 1:2     Prescale value

Timer0(8-bit mode) Block Diagram

timer0-8-bit-mode.png

Operation

Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected.

If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter.

Timer0 (16-bit mode) Block Diagram

timer0-16-bit-mode.png

Operation

TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writable (refer to Figure 11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.

Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count.

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. 

TIMER1 Module

The Timer1 timer/counter module incorporates these features:

  • Software selectable operation as a 16-bit timer or counter
  • Readable and writable 8-bit registers (TMR1H and TMR1L)
  • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options
  • Interrupt-on-overflow
  • Reset on CCP Special Event Trigger
  • Device clock status flag (T1RUN)

A simplified block diagram of the Timer1 module is shown in Figure  The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register. It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). 

T1CON

76543210
RD16T1RUNT1CKPS1T1CKPS0T1OSCENT1SYNCTMR1CSTMR1ON
BitDescription
7RD16: 16-Bit Read/Write Mode Enable bit
  • 1 = Enables register read/write of TImer1 in one 16-bit operation
  • 0 = Enables register read/write of Timer1 in two 8-bit operations 
6T1RUN: Timer1 System Clock Status bit
  • 1 = Device clock is derived from Timer1 oscillator
  • 0 = Device clock is derived from another source
5-4T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
  • 11 = 1:8 Prescale value
  • 10 = 1:4 Prescale value
  • 01 = 1:2 Prescale value
  • 00 = 1:1 Prescale value 
3T1OSCEN: Timer1 Oscillator Enable bit
  • 1 = Timer1 oscillator is enabled
  • 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. 
2T1SYNC: Timer1 External Clock Input Synchronization Select bit
  • When TMR1CS = 1
    • 1 = Do not synchronize external clock input
    • 0 = Synchronize external clock input
  • When TMR1CS = 0 
    • This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. 
1TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) 
0TMR1ON: Timer1 On bit
  • 1 = Enables Timer1
  • 0 = Stops Timer1

Timer1 Block Diagram

TIMER1-Block-Diagram.png

Timer1 Operation

Timer1 can operate in one of these modes:

  • Timer
  • Synchronous Counter
  • Asynchronous Counter

The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.

Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a lowpower circuit rated for 32kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure12-3. Table12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.

Timer1-as-Oscillator.png
 

Timer2 Module

The Timer2 module timer incorporates the following features:

  • 8-Bit Timer and Period registers (TMR2 and PR2, respectively)
  • Readable and writable (both registers)
  • Software programmable prescaler (1:1, 1:4 and 1:16)
  • Software programmable postscaler (1:1 through 1:16)
  • Interrupt on TMR2 to PR2 match
  • Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register (Register13-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure.

T2CON

76543210
-T2OUTPS3T2OUTPS2T2OUTPS1T2OUTPS0TMR2ONT2CKPS1T2CKPS0
BitDescription
7Unimplemented
6-3

 T2OUTPS<3:0>: Timer2 Output Postscale Select bits

  • 0000 = 1:1 Postscale
  • 0001 = 1:2 Postscale
  • 0010 = 1:3 Postscale
  • 0011 = 1:4 Postscale
  • 0100 = 1:5 Postscale
  • 0101 = 1:6 Postscale
  • 0110 = 1:7 Postscale
  • 0111 = 1:8 Postscale
  • 1000 = 1:9 Postscale
  • 1001 = 1:10 Postscale
  • 1010 = 1:11 Postscale
  • 1011 = 1:12 Postscale
  • 1100 = 1:13 Postscale
  • 1101 = 1:14Postscale
  • 1110 = 1:15 Postscale
  • 1111 = 1:16 Postscale 
2TMR2ON: Timer2 On bit
  • 1 = Timer2 is on
  • 0 = Timer2 is off 
1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
  • 00 = Prescaler is 1
  • 01 = Prescaler is 4
  • 1x = Prescaler is 16

Timer2 Block Diagram

Timer-2-block-diagram.png

Timer2 Operation

In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by16 prescale options; these are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 13.2 “Timer2 Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written.

Timer2 Interrupt

Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>).

Timer2 Output

The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can optionally be used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section “Master Synchronous Serial Port (MSSP) Module”.

Timer3 Module

The Timer3 module timer/counter incorporates these features:

  • Software selectable operation as a 16-bit timer or counter
  • Readable and writable 8-bit registers (TMR3H and TMR3L)
  • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options
  • Interrupt-on-overflow
  • Module Reset on CCP Special Event Trigger A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register. It also selects the clock source options for the CCP modules “CCP Modules and Timer Resources” for more information. 

T3CON register

76543210
RD16T3CCP2T3CKPS1T3CKPS0T3CCP1T3SYNCTMR3CSTMR3ON
BitDescription
7RD16: 16-Bit Read/Write Mode Enable bit
  • 1 = Enables register read/write of TImer3 in one 16-bit operation
  • 0 = Enables register read/write of Timer3 in two 8-bit operations 
6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the capture/compare clock source for the CCP modules 01 = Timer3 is the capture/compare clock source for CCP2; Timer1 is the capture/compare clock source for CCP1 00 = Timer1 is the capture/compare clock source for the CCP modules 
5-4T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value 
3T1OSCEN: Timer1 Oscillator Enable bit
  • 1 = Timer1 oscillator is enabled
  • 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. 
2T3SYNC: Timer3 External Clock Input Synchronization Select bit
  • When TMR3CS = 1
    • 1 = Do not synchronize external clock input
    • 0 = Synchronize external clock input
  • When TMR3CS = 0 
    • This bit is ignored. Timer1 uses the internal clock when TMR3CS = 0. 
1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) 
0TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3

Timer3 block Diagram

Timer3-block-Diagram.png

Timer3 Operation

Timer3 can operate in one of three modes:

  • Timer
  • Synchronous Counter
  • Asynchronous Counter

The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.

Using the Timer1 Oscillator as the Timer3 Clock Source

The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section 12.0 “Timer1 Module”.

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>)

Resetting Timer3 Using the CCP Special Event Trigger

If either of the CCP modules is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will reset Timer3. It will also start an A/D conversion if the A/D module is enabled (see Section 15.3.4 “Special Event Trigger” for more information). The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a Period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will take precedence.

References

  • Created, Edited and Notes by Prof. Sujit Wagh, SKNCOE, Pune
  • WikiNote Foundation
Tags:
Created by Sujit Wagh on 2017/09/24 18:46
Translated into en by Sujit Wagh on 2017/09/24 18:49