Block Diagram of 8051 Microcontroller

Updated on 2017/08/02 11:59

Syllabus

  • 8051 Microcontroller: Block diagram and explanation

Introduction to 8051

The 8051 microcontroller is a very popular 8-bit microcontroller introduced by Intel in the year 1981 and it has become almost the academic standard now a days. The 8051 is based on an 8-bit CISC core with Harvard architecture. Its 8-bit architecture is optimized for control applications with extensive Boolean processing. It is available as a 40-pin DIP chip and works at +5 Volts DC.

Salient Features of 8051

  1. 4 KB on chip program memory (ROM or EPROM)
  2. 128 bytes on chip data memory (RAM)
  3. 8-bit data bus
  4. 16-bit address bus
  5. 32 general purpose registers each of 8 bits
  6. Two - 16 bit timers T0 and T1
  7. Five Interrupts (3 internal and 2 external)
  8. Four Parallel ports each of 8-bits (PORT0, PORT1, PORT2, PORT3) with a total of 32 I/O lines
  9. One 16-bit program counter and One 16-bit DPTR ( data pointer)
  10. One 8-bit stack pointer
  11. One Microsecond instruction cycle with 12 MHz Crystal
  12. One full duplex serial communication port

Architecture Diagram

8051 Architecture

The architecture of the 8051 microcontroller can be understood from the block diagram. It has Harward architecture with RISC (Reduced Instruction Set Computer) concept.
The block diagram of 8051 microcontroller is shown. It consists of:

  • an 8-bit ALU
  • one 8-bit PSW (Program Status Register)
  • A and B registers
  • one 16-bit Program counter
  • one 16-bit Data Pointer Register (DPTR)
  • 128 bytes of RAM and 4kB of ROM and four parallel I/O ports each of 8-bit width

Architecture Explained

Arithmetic Logic Unit (ALU)

  • 8-bit ALU
  • can perform all the 8-bit arithmetic and logical operations in one machine cycle
  • The ALU is associated with two registers A & B which are special function registers which hold the results of many arithmetic and logical operations.

A Register

  • It is also called the Accumulator and as it’s name suggests, it is used as a general register to accumulate the results of a large number of instructions.
  • By default it is used for all mathematical operations and also data transfer operations between CPU and any external memory.

B Register

  • It is mainly used for multiplication (MUL AB) and division ( DIV AB) operations along with A register. 
  • It has no other function other than as a location where data may be stored.

The R registers

  • The "R" registers are a set of eight registers that are named R0, R1 up to and R7.
  • These registers are used as auxillary registers in many operations.
  • These registers are also used to temporarily store values.

Program Counter (PC)

  • 16-bit program counter
  • It always points to the address of the next instruction to be executed. After execution of one instruction the program counter is incremented to point to the address of the next instruction to be executed.
  • Contents of PC are placed on address bus to find and fetch the desired instruction.
  • Since the PC is 16-bit width, 8051 can access program addresses from 0000H to FFFFH, a total of 6kB of code.

Stack Pointer Register (SP)

  • 8-bit register which stores the address of stack top. i.e the Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from.
  • When a value is pushed onto the stack, the 8051 first increments the value of SP and then stores the value at the resulting memory location.
    Similarly when a value is popped off the stack, the 8051 returns the value from the memory location indicated by SP, and then decrements the value of SP.
    Since the SP is only 8-bit wide it is incremented or decremented by two.
  • SP is modified directly by six instructions: PUSH, POP, ACALL, LCALL, RET, and  RETI.
  • It is also used intrinsically whenever an interrupt is triggered.

Stack

  • The CPU needs this storage area as there are only limited number of registers.
  • It is a part of RAM used by the CPU to store information temporarily. This information may be either data or address.
  • The register used to access the stack is called the Stack Pointer which is an 8-bit register. So,it can take values of 00 to FF H.
  • When the 8051 is powered up, the SP register contains the value 07. It means the RAM location value 08 is the first location being used for the stack by the 8051 controller.
  • There are two important instructions to handle this stack.
    1. PUSH: The loading of data from CPU registers to the stack is done by PUSH
    2. POP: The loading of contents of the stack back into aCPU register is done by POP

      Example:
      MOV R6 , #35 H
      MOV R1 , #21 H
      PUSH 6
      PUSH 1

      In the above instructions the contents of the Registers R6 and R1 are moved to stack and they occupy the 08 and 09 locations of the stack. Now the contents of the SP are incremented by two and it is 0A.
      Similarly POP 3 instruction pops the contents of stack into R3 register. Now the contents of the SP is decremented by 1.
  • In 8051 the RAM locations 08 to 1F (24 bytes) can be used for the Stack.
    In any program if we need more than 24 bytes of stack, we can change the SP point to RAM locations 30 - 7F H. This can be done with the  instruction MOV SP , # XX.

Data Pointer Register (DPTR)

  • It is a 16-bit register which is the only user-accessible
  • As the name suggests, DPTR is used to point to data.
  • It is used by a number of commands which allow the 8051 to access external memory. When the 8051 accesses external memory it will access external memory at the address indicated by DPTR.
  • DPTR can also be used as two 8-registers DPH and DPL.

Program Status Register (PSW)

  • The 8051 has a 8-bit PSW register which is also known as Flag register. In the 8-bit register only 6-bits are used by 8051. Two unused bits are user definable bits.
  • In the 6-bits four of them are conditional flags. They are Carry - CY, Auxiliary Carry - AC, Parity - P and Overflow - OV. These flag bits indicate some conditions that resulted after an instruction was executed. 
PSW7PSW6PSW5PSW4PSW3PSW2PSW1PSW0
CYACF0RS1RS0OV--P

The meaning of various bits of PSW register is shown below:

Bit DesignationBit NumberBit Function
CYPSW.7Carry Flag
ACPSW.6Auxiliary Carry Flag
FOPSW.5Flag 0 available for general purpose
RS1PSW.4Register Bank select bit 1
RS0PSW.3Register bank select bit 0
OVPSW.2Overflow flag
---PSW.1User difinable flag
PPSW.0

Parity flag; set/cleared by hardware

The selection of the register Banks and their addresses are given below.

RS1

RS0

Register Bank

Address

0

0

0

00H-07H

0

1

1

08H-0FH

1

0

2

10H-17H

1

1

3

18H-1FH

Special Function Registers (SFRs)

  • Certain registers which use RAM addresses from 80h to FF H and they are meant for certain specific operations. These registers are called Special Function Registers (SFRs).
  • Some of these registers are bit addressable.
  • Some of them are related to I/O ports (P0, P1, P2 and P3).
  • Some of them are meant for control operations (TCON, SCON, PCON)
  • Remaining are the auxillary SFRs, in the sense that they don't directly configure the 8051.

The list of SFRs and their functional names are given below.

Sr. No.

Symbol

Name of SFR

Address (Hex)

1

ACC*

Accumulator

0E0

2

B*

B-Register

0F0

3

PSW*

Program Status word register

0DO

4

SP

Stack Pointer Register

81

5

 

DPTR

DPL

Data Pointer - low byte

82

DPH

Data Pointer - high byte

83

6

P0*

Port 0

80

7

P1*

Port 1

90

8

P2*

Port 2

0A

9

P3*

Port 3

0B

10

IP*

Interrupt Priority control

0B8

11

IE*

Interrupt Enable control

0A8

12

TMOD

Timer Mode Register

89

13

TCON*

Timer Control Register

88

14

TH0

Timer 0 - Higher byte

8C

15

TL0

Timer 0 - Lower byte

8A

16

TH1

Timer 1 - Higher byte

8D

17

TL1

Timer 1 - Lower byte

8B

18

SCON*

Serial Control Register

98

19

SBUF

Serial Buffer Register

99

20

PCON

Power Control Register

87

The * indicates the bit addressable SFRs.

References

  • Notes by Prof. Sujit Wagh, SKNCOE, Pune
  • WikiNote Foundation
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Created by Vishal E on 2017/08/02 11:59