Syllabus

This point is not mentioned in University syllabus but is asked more ofter in examination.

Features of NVIC

This module provides the processor's outstanding interrupt handling abilities.

  1. Non-Maskable Interrupt (NMI) and 32 general purpose interrupts with 8 levels of premption priority.
  2. It can be configured to anywhere between 1 and 240 physical interrupts with up to 256 levels of priority through simple synthesis choices.
  3. The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by exerting higher priority.
  4. It also supports dynamic reprioritisation of interrupts. Priority levels can be changed by software during run time. Interrupts that are being serviced are blocked from further activation until the interrupt service routine is completed, so their priority can be changed without risk of accidental re-entry.

Stack based Exception/Interrupt Handling Procedure

  • The Cortex-M3 processor uses a re-locatable vector table that contains the address of the function to be executed for a particular interrupt handler.
  • On accepting an interrupt, the processor fetches the address from the vector table through the instruction bus interface.
  • The vector table is located at address zero at reset, but can be relocated by programming a control register
  • To reduce gate count and enhance system flexibility the Cortex-M3 uses a stack based exception model.
    1. When an exception takes place, the Program Counter, Program Status Reistger, Link Register, the R0-R3,R12 general purpose register as are automatically pushed on to the stack.
    2. The data bus stacks the registers whilst the instruction bus identifies the exception vector from the vector table and fetches the first instruction of the exception code.
    3. Once the stacking and instruction fetch are completed, the interrupt service routine or fault handler is executed, followed by the automatic restoration of the registers to enable the interrupted program to resume normal execution.

Tail-Chaining in NVIC

Case I: Back-to-back interrupts

  • In the case of back-to-back interrupts, traditional systems would repeat the complete state save and restore cycle twice, resulting in higher latency.
  • The Cortex-M3 processor simplifies moving between active and pending interrupts by implementing tail-chaining technology in the NVIC hardware.
  • Tail-chaining achieves much lower latency by replacing serial stack pop and push actions that normally take over 30 clock cycles with a simple 6 cycle instruction fetch.
  • The processor state is automatically saved on interrupt entry, and restored on interrupt exit, in fewer cycles than a software implementation, significantly enhancing performance in sub-100MHz systems.

NVIC-tail-chaining.jpg

Case-I: Back to Back Interrupt Handling(Tail chaining)

Image source: Google sites - iprinceps 

Case-II: Late Arrival of High priority interrupt during push

  • Tail-chaining technology in the NVIC supports interrupts that occur back-to-back, but there could be cases where an interrupt of higher priority could also occur during the stacking (Push) or state restore (Pop) stages of the interrupt being serviced.
  • In traditional ARM7 based systems, these stages need to complete before the pending interrupt can take over. The Cortex-M3 NVIC, on the other hand, provides deterministic response to these possibilities with support for late arrival and pre-emption. 
  • In case of the late arrival of a higher priority interrupt during the execution of the stack Push for a previous interrupt, the NVIC immediately fetches a new vector address to service the pending interrupt, as shown below.

NVIC-late-arrival-tail-chaining.jpg

Case-II: Late Arrival of High priority interrupt during push

Image source:-Google sile: iprinceps 

Case III: Arrival of interrupt during POP

  • NVIC abandons a stack Pop if an exception arrives and services the new interrupt immediately as shown below.
  • By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.

NVIC-arrival-during-POP-tail-chaining.jpg

Case III-Arrival of interrupt during POP

Image source:-Google site: iprinceps 

Power-management through NVIC

  • The NVIC also implements the power-management scheme of the Cortex-M3 processor that supports integrated sleep modes.
  • The Sleep Now mode is invoked by either the Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions that immediately puts the core into low-power state pending an exception.
  • The Sleep On Exit mode puts the system into low-power mode as soon as it exits the lowest priority interrupt-service routine.
  • The core stays in sleep state until another exception is encountered. Since only an interrupt can exit this mode, the system state is not restored.
  • The SLEEPDEEP bit of the system control register, if set; can be used to clock gate the core and other system components for optimal power savings.
  • The NVIC also integrates a System Tick (SysTick) timer, which is a 24-bit count-down timer that can be used to generate interrupts at regular time intervals, proving an ideal heartbeat to drive a Real Time OS or other scheduled tasks.

References

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Created by 1stVolunteer on 2017/06/21 11:11