Interfacing: ADC using VIC

Updated on 2017/06/19 20:59


Interfacing the peripherals to LPC2148: on-chip ADC using interrupt (VIC)

Interrupt Structure

  • ARM7 Processor hardware interrupt inputs: 2, (FIQ. IRQ)
  • LPC2148 external interrupt inputs: 4 (available on 9 pins)
  • Processor and on-chip user peripherals generate interrupts
  • LPC2148 uses ARM PrimeCell (PL190) Vectored Interrupt Controller for managing interrupts.
  • PL190 is interfaced to ARM core through the fast AHB bus

When interrupt occurs:

  1. VIC identifies the source of interrupts
  2. Passes requests on interrupt request pins as per the configuration
  3. If more than one interrupt occurs at a time, VIC resolves priority

Vectored Interrupt Controller (VIC)

  • 32 interrupt request inputs, LPC2148 uses 22 of 32 interrupts
  • Categorizes into Fast Interrupt Request, Vectored IRQ, Non Vectored IRQ interrupts
  • Any of the 22 interrupts can be assigned to FIQ / VIRQ / NVIRQ
  • FIQ: Generally, only one interrupt is assigned, VIC provides ISR address. If more than one is assigned to FIQ, VIC combines all, generates VICFIQ, provides only one ISR address for all FIQ (Non-Vectored FIQ) .
  • VIC has 16 VIRQ slots, Slot-0 to Slot-15. Any IRQ configured interrupts can be assigned to any slot. Priorities are in the order of slot number.
  • Interrupts configured as IRQ, not assigned any VIRQ slot, is assigned as NVIRQ
  • VIRQ & NVIRQ interrupts are combined and VICIRQ is generated
  • Programs can handle 1 FIQ, 16 VIRQ, 1 NVIRQ (total 18) interrupts


VIC Registers (only important listed)

  1. VICIntSelect: High, Low bits select interrupts as FIQ, IRQ respectively
  2. VICIntEnable: High bit enables FIQ or IRQ classified interrupts
  3. VICIntEnClr: High bit disables FIQ or IRQ classified, enabled interrupts
  4. VICSoftInt: Generates any interrupt by software. High bit generates corresponding interrupt
  5. VICSoftIntClr: Clears a bit in Software Interrupt register
  6. VICIRQStatus: A high bit indicates corresponding IRQ classified, enabled IRQ interrupt is active
  7. VICFIQStatus: A high bit indicates corresponding FIQ classified, enabled IRQ interrupt is active
  8. VICVectAddr: Holds ISR addr of active interrupt. Writing any value indicates End of Interrupt
  9. VICVectAddr0VICVectAddr15: Hold ISR addresses for slots 0 to 15
  10. VICVectCntl0VICVectCntl15: Control 16 IRQ slots, assigns sources to each slot. Bit [4:0] selects VIC channel, bit [5] select VIRQ / NVIRQ, high / low bit provides dedicated / default ISR addr.

Programming VIC registers

  • VICIntSelect: Set / reset the bits for FIQ / IRQ classification
  • VICVectCtrlx: Assign VIRQ slot ‘x’ to IRQ classified interrupt
  • VICVectAddrx: Write ISR addr of VIRQ interrupt assigned to slot ‘x’
  • VICIntEnable: Enable interrupts 

Programming VIC registers: Examples

1) Programming VICIntSelect register

VICIntSelect = 0x0000 0010; // enable VIC Timer-0 channel as VFIQ interrupt  (by default all interrupts are VIRQ enabled) //

2) Programming VICVectCntlx register 

VICVectCntl0=(0x01<<5)|0x04; // assign VIRQ Slot-0 to Timer-0, enable Slot-0  (bit[4:0] is channel no. bit[5] enables slot) //

3) Programming VICVectAddrx register

void Timer0ISR(void) __irq;      // declare prototype for ISR//
unsigned long int T0vectaddr;    // declare variable to hold Timer-0 ISR address//
T0vectaddr=(unsigned)Timer0ISR; // place ISR address in variable//
VICVectAddr0 = T0vectaddr;      // write ISR address into Slot-0 VectAddr reg//

4) Programming VICIntEnable register

VICIntEnable = 0x00000010;    // enable Timer-0 interrupt//

Handling FIQ interrupts

  • Branch instruction at 0x0000001C uses address of FIQ handler directly and goes to FIQ routine. This reduces interrupt latency. 
  • If more than one interrupt are assigned as FIQ, the handler routine identifies the source of interrupt. This increases interrupt latency. 
  • Executes codes respective of identified interrupts. 
  • Clears flags set by peripherals in their interrupt registers o End of interrupt.

Handling IRQ interrupts

  • On interrupt, processor executes branch instruction from interrupt vector table at 0x 00000018 and branches to IRQ handler routine 
  • Reads VICVectAddr reg that holds address of highest priority pending VIRQ Slot-x interrupt. If no slot is assigned, it holds address of default vect address 
  • Branches to handler routine. 
  • Reads interrupt register of the peripheral, identifies actual source, executes codes respective of the interrupt. 
  • Clears interrupt flags set by peripherals in their interrupt registers. 
  • Writes a dummy word into VICVectAddr register to indicate EoI, to clear respective interrupt in VIC interrupt priority hardware. 
  • Returns back to interrupted program, re-enables interrupts.

Analog Digital Converter

Features of ADC

  • ADC0 (6 Ch), ADC1 (8 Ch) 
  • Type: 10-bit, SA type, 
  • Supports burst mode (repeated conversion at 3-bit to 10-bit resolution) 
  • Supports simultaneous conversion of both ADCs 
  • Conversion time: 2.44 s, 
  • SoC by software control, on timer match, transition on a pin 
  • Range: 0 V – VREF (+3.3 V) 
  • Max. clock freq is 4.5 MHz, (by programming ADCCON) 

ADC Interfacing Diagram


Block Explanation
ADC0AD0.1Channel 1P0.28
AD0.2Channel 2P0.29
AD0.3Channel 3P0.30
AD0.4Channel 4P0.25
AD0.6Channel 6P0.4
AD0.7Channel 7P0.5
ADC1AD1.0Channel 0


AD1.1Channel 1


AD1.2Channel 2


AD1.3Channel 3


AD1.4Channel 4


AD1.5Channel 5


AD1.6Channel 6


AD1.7Channel 7P0.22

ADC Registers

1) Control Register

Selects channel, clock freq, resolution, conversion mode, method of issue of SoC, edge for conversion 

  • 7-0 SEL: Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8one
  • 15-8 CLKDIV: The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
    • The A/D Converters on the LPC2148 is also called as The conversion speed is selectable by the user

 A/D Clock frequency= [Pclk/(CLKDIV+1)]  .....................<=4.5 MHz

  • 16  BURST : The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed.
    • Remark: START bits must be 000 when BURST = 1 or conversions will not start.
  • 19-17 CLKS: This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the RESULT bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
CLKS field - 19-18-17No. of Clock cycles used per bit conversion
00011 clocks cycles / 10 bit conversion
00110 clocks/ 9 bits
0109 clocks/ 8 bits
0118 clocks/ 7 bits
1007 clocks/ 6 bits
1016 clocks/ 5 bits
1105 clocks/ 4 bits
1114 clocks/ 3 bits
  • 21 PDN   
    • PDN=1 The A/D converter is operational.
    • PDN=0 The A/D converter is in power-down mode.

2) A/D Global Start Register (ADxGSR)

  • Used to initiate simultaneous conversion on both ADCs 

3) A/D Status Register (ADxSTAT)

  • Allows simultaneous checking of status of all A/D channels
  • Contains done, overrun, interrupt flags 

4) A/D Data Registers (ADR0 – ADR7)

  • Contains most recent converted data and EoC status on respected ch

5) Global Data Register

  • Contains done bit, most converted data, ch number 
DONEOVERRUNReserved10 bit A/D RESULTReserved
  • DONE (Bit 31)
    • DONE= 1  ;when an A/D conversion is complete.
    • D0NE=0  ;A/D conversion is in progress

For accurate results, you need to wait until this value is 1 before reading the RESULT bits. (Please note that this value is cleared when you read this register.)

  • OVERRUN (Bit 30)

While not relevant to the examples used in this tutorial, this value with be 1 if the results of one or more conversions were lost when converting in BURST mode. See the User's Manual for further details.  (As with DONE, this bit will be cleared when you read this register.)

  • RESULTS (Bits 15..6)

If DONE is 1 (meaning the conversion is complete), these 10 bits will contain a binary number representing the results of our analog to digital conversion. It works by measuring the voltage on the analog input pin divided by the voltage on the Vref pin.

Analog Input10-bit Digital outputDigital Output in HEX
0V0000 0000 00 B000H
3.3V1111 1111 11 B3FFH

Zero means that the voltage on the analog input pin was less than, equal to or close to GND (Vssa), and 0x3FF (or 0011 1111 1111) indicates that the voltage on the analog input pin was close to, equal to or greater than the the voltage on the Vref pin.  Anything value between these two extremes will be returned as a 10-bit number (between 0 and 1023).  

6) Interrupt Enable Register

  • Enables interrupt on EOC channel
  • Programming ADC registers – Examples (Construction of control words


  1. Select ADC-0, Channel-1, Clock frequency 3.75 MHz (let PCLK is 15 MHz), burst mode repeated conversion) and 10-bit resolution. Power-up ADC and issue start of conversion.
    Solution: AD0CR    = 0x01210302; // configure SEL, CLKDIV, BURST CLKS & PDN bit fields set START, signal start of conversion
  2. Select ADC–1, Channels 0 to 7, clock frequency 4.5 MHz (assume PCLK is 30 MHz), burst mode repeated conversion, 8-bit resolution.


  • nxp datasheet
  • LPC2148 Architecture and Programming - Dr. N. Mathivanan
Created by Vishal E on 2017/04/14 14:07