Interfacing: GSM and GPS using UART

Updated on 2017/06/19 20:50

Syllabus

Interfacing the peripherals to LPC2148:
GSM and GPS using UART

UART0

Features

  • 16 byte Receive and Transmit FIFOs
  • Register locations conform to ‘550 industry standard.
  • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
  • Built-in fractional baud rate generator with auto-bauding capabilities.
  • Mechanism that enables software and hardware flow control implementation.

Pin description

Pin  Type     Description
RXD0InputSerial Input: Serial receive data.
TXD0OutputSerial Output: Serial transmit data.

UART1

Features

  • UART1 is identical to UART0, with the addition of a modem interface.
  • 16 byte Receive and Transmit FIFOs.
  • Register locations conform to ‘550 industry standard.
  • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
  • Built-in fractional baud rate generator with autobauding capabilities.
  • Mechanism that enables software and hardware flow control implementation.
  • Standard modem interface signals included with flow control (auto-CTS/RTS) fully
  • supported in hardware (LPC2144/6/8 only).

Pin description

Pin  Type     Description
RXD1InputSerial Input: Serial receive data.
TXD1OutputSerial Output: Serial transmit data.
CTS1InputClear To Send
DCD1InputData Carrier Detect
DSR1InputData Set Ready
DTR1OutputData Terminal Ready
RI1InputRing Indicator
RTS1OutputRequest To Send

UART0

Block Diagram

UART_Block_Diagram.PNG

UART Registers

U0FCR (FIFO Control Register)
  • 8-BIT Byte Addressable register
  • This reg is used to enable TX & RX FIFO functionalities
  • U0FCR=0x07 is like SCON reg
U0FCRFIFO Control Register-----TX FIFO ResetRX FIFO ResetFIFO Enable
U0LCR (Line Control Register)
  • 8-BIT byte addressable register

UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description 

BitSymbolValueDescriptionReset Value
1:0


 
Word Length Select


 
005 bit character length0


 
016 bit character length
107 bit character length
118 bit character length
2
 
Stop Bit Select
 
01 stop bit0
 
12 stop bits (1.5 if U0LCR[1:0]==00)
3
 
Parity Enable
 
0Disable parity generation and checking0
 
1Enable parity generation and checking
5:4


 
Parity Select


 
00Odd parity. Number of 1s In the transmitted character and the attached parity bit will be odd.0


 
01Even Parity. Number of is in the transmitted character and the attached parity bit will be even.
10Forced "1" stick parity.
11Forced "0" stick parity.
6
 
Break Control
 
0Disable break transmission0
 
1Enable break transmission. Output pin UARTO TXD Is forced to logic 0 when UOLCR[6] Is active high. 
7
 
Divisor Latch Access Bit (DLAB)
 
0Disable access to Divisor Latch0
1Enable access to Divisor Latch

DLAB (Divisor Latch Buffer)

One high-low pulse across DLAB bit indicates baud rate is successfully loaded.

  • DLAB=1  baud rate is loading
  • DLAB=0  After loading baud rate DLAB must be zero.
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U0LSR (Line Status Register)
  • 8-bit byte addressable register
  • Consists of different flag bits, TI interrupt & RI interrupt flag bit
UART0 Line Status Register
BitSymbolValueDescriptionReset value
0Receiver Data Ready (RDR) U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIFO is empty. 0
0U0RBR is empty.
1U0RBR contains valid data.
1

 
Overrun Error (OE)

 
 The overrun error condition is set as soon as it occurs. An U0LSR read clears U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled and the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will not be overwritten and the character in the UART0 RSR will be lost. 0

 
0Overrun error status is inactive.
1Overrun error status is active.
2
 
Parity Error
 
 

When the parity bit of a received character is in the wrong state, a parity error occurs. An U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on U0FCR(0).

Note: A parity error is associated with the character at the top of the UART0 RBR FIFO.

0
 
0Parity error status is Inactive.
3

 
Framing Error (FE)

 
 

When the stop bit of a received character is a logic 0. a framing error occurs. 0 An U0LSR read dears U0LSR[3]. The time of the framing error detection is dependent on U0FCR0. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error.

Note: A framing error is associated with the character at the top of the UART0 RBR FIFO.

0

 
0Framing error status is inactive. 
1Framing error status is active. 
4

 
Break Interrupt (BI)

 
 

When RXD0 is held in the spacing state (all 0's) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD0 goes to marking state (all 1s). An U0LSR read clears this status bit. The time of break detection is dependent on U0FCR(0).

Note: The break interrupt is associated with the character at the top of the UART0 RBR FIFO.

0

 
0Break interrupt status is inactive. 
1Break interrupt status is active. 
5

 
Transmitter Holding Register Empty (THRE)

 
 THRE is set immediately upon detection of an empty UART0 THR and is 1
cleared on a U0THR write. 
1

 
0U0THR contains valid data. 
1U0THR is empty.
6

 
Transmitter Empty (TEMT) 

 
 TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when either the U0TSR or the U0THR contain valid data.1

 
0U0THR and/or the U0TSR contains valid data. 
1U0THR and the U0TSR are empty. 
7

 
Error in RX FIFO (RXFE) 

 
 UOLSR(7) is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is read and there are no subsequent errors in the UART0 FIFO.0
 
0U0RBR contains no UART0 RX errors or U0FCR[0]=0.
1UART0 RBR contains at least one UART0 RX error.
6th bit of LSR is TI flag bit
While(!(U0LSR&0x40));//Monitoring TI bit syntax

0th bit of LSR is RI flag bit
While(!(U0LSR&0x10));//Monitoring RI bit syntax
DLR (Divisor Latch Register)
  • DLR is 16-bit register
  • Used to load baud rate
  • As the baud rate is 8-bit value, divide DLR into two parts DLM & DLL (8-bit each)

For 9600 baud rate
U0DLL=0x63;     //(Pclk=12Mhz)
U0DLM=0x00

U0DLL:U0DLM=[Pclk/16*Desired Baud rate]

U0THR (Transmit Hold Register)
  • 8-bit byte addressable reg
  • Data can be loading to U0THR, whenever transmitting data

U0THR=‘A’   //THR buffer register is used only for transmitting

U0RBR (UART0 Receive Buffer Register)
  • 8-bit byte addressable reg
  • Data can be loading into U0RBR, whenever receiving data.

a = U0RBR   //RBR buffer register is used only for transmitting

Program to receive and transmit data using UART0

#include<LPC21xx.h>
void main()
{
char a;
 PINSEL0=0x00000005;//P0.0 as TxD0 & P0.1 as RxD0
U0LCR=0x83;//8 -bit character length,DLAB=1
U0DLM=0x00;//
U0DLL=0x61;// Baud rate=9600
U0LCR=0x03;// DLAB=0; to load baud rate value

while(1)
  {
  while(!(U0LSR&0x01));  //monitoring TI flag
  a=U0RBR;
  
  while(!(U0LSR&0x20));  // monitoring RI flag
  U0THR=a;
  }
}

Global System for Mobile Communications

  • GSM (Global System for Mobile Communications) is the technology that underpins most of the world's mobile phone networks.
  • GSM is an open, digital cellular technology used for transmitting mobile voice and data services.
  • GSM operates in the 900MHz and 1.8GHz bands GSM supports data transfer speeds of up to 9.6 kbps, allowing the transmission of basic data services such as SMS.
  • The SIM300 module is a Triband GSM/GPRS solution in a compact plug in module featuring an industry-standard interface

Features of GSM MODEM

  • Single supply voltage 3.2v-4.5v
  • Typical power consumption in SLEEP Mode: 2.5mA.
  • SIM300 tri-band
  • MT,MO,CB, text and PDU mode, SMS storage: SIM card
  • Supported SIM Card :1.8V,3V

GSM_MODULE_SIM300.png

GSM_MODULE_SIM900.png

GSM_Block_Diagram.png

GSM Module

  • GSM/GPRS module is used to establish communication between a computer and a GSM-GPRS system.
  • Global System for Mobile communication (GSM) is an architecture used for mobile communication in most of the countries.
  • Global Packet Radio Service (GPRS) is an extension of GSM that enables higher data transmission rate

GSM Mobile Vs GSM Module

  • A GSM mobile is a complete system in itself with embedded processors that are dedicated to provide an interface between the user and the mobile network.
  • The AT commands are served between the processors of the mobile termination and the terminal equipment.
  • The mobile handset can also be equipped with a USB    interface to connect with a computer, but it may or may not support AT commands from the computer or an external processor/controller.
  • The GSM/GPRS module, on the other hand, always needs a computer or external processor/controller to receive AT commands from.
  • GSM/GPRS module itself does not provide any interface between the user and the network, but the computer to which module is connected is the interface between user and network.
  • An advantage that GSM/GPRS modules offer is that they support concatenated SMS which may not be supported in some GSM mobile handsets
  • Applications of GSM/GPRS module The GSM/GPRS module demonstrates the use of AT commands. They can feature all the functionalities of a mobile phone through computer like making and receiving calls, SMS, MMS etc. These are mainly employed for computer based SMS and MMS services.

AT Commands

  • AT commands are used to control MODEMs.AT is the abbreviation for Attention.
  • These commands come from Hayes commands that were used by the Hayes smart modems.
  • The Hayes commands started with AT to indicate the attention from the MODEM.
  • The dial up and wireless MODEMs need AT commands to interact with a computer.
  • AT commands with a GSM/GPRS MODEM
GSM AT Commands and their functions
AT CommandFunction of AT Command
ATDDial
AT+CGMSSend SMS Message
AT+CMSSSend SMS Message from storage
AT+CMGLList SMS Messages
AT+CMGRRead SMS Messages
AT+CSCA?Service Centre Address
AT+CPMSTo choose storage from ME or SM
AT+IPR=0To choose auto from baud rate
AT+SMGF=To choose PDU Mode or Text Mode

Interfacing of GSM Module

Interfacing Diagram

GSM_Interfacing_lpc2148.png

Pin assignment with LPC 2148

Pin Assignments
 

UART DB-9 Connector

LPC2148 Processor Lines

UART0 (P1) ISP PGM

TXD-0P0.0
RXD-0P0.1

UART1 (P2)

TXD-1P0.8
RXD-1P0.9

Algorithm for GSM module interfacing with LPC2148

1) Start

2) Initialise UART0 or UART1 serial interfface using following i nstruction

PINSEL0=0X0000 0005;//Enable P0.0-TxD0,P0.1-RxD0
U0LCR=0X83;  //8-BIT Character lenth,NO parity,1 stop bit
U0DLL=97; //Baud rate=9600@PCLK=15Mhz
U0LCR=0X03;//Dlab=0

3) Transmit different AT commands through UART module using instruction

while(!(U0LSR&0X20));//Monitor TI flag

4) If transmission buffer is Empty,Transmit AT commands 

U0THR=ch;

5) Provide delay while transmitting each command

6) To transmit a single character use PUTCH function & to transmit a string use PUTS function 

7) END

References

  • WikiNote Foundation
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Created by Sujit Wagh on 2017/04/14 16:52