Interfacing the peripherals to LPC2148: EEPROM using I2C

I2C Module

Features of I2C module

  • Standard I2C compliant bus interfaces that may be configured as Master, Slave, or Master/Slave.
  • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
  • Programmable clock to allow adjustment of I2C transfer rates.
  • Bidirectional data transfer between masters and slaves.
  • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
  • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
  • The I2C bus may be used for test and diagnostic purposes.


Interfaces to external I2C standard parts

  • Serial RAMs
  • LCDs
  • Tone generators 

I2C Bus Configuration


Pin Description

PinTypeDescriptionLPC2148 Pins
SDA0/1Input/OutputI2C Serial DataP0.3 and P0.14
SCL0/1Input/OutputI2C Serial ClockP0.2 and P0.11

I2C Registers

Summary of I2C Registers
Generic NameDescriptionAccessReset valueI2Cn Register name & Address
I2CONSETI2C Control Set Register. When a one is written to a bit of this register. the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. R/W0x00

I2C0CONSET - 0xE001 C000

I2C1CONSET - 0xE005 C000

I2STATI2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.RO0xF8

I2C0STAT - 0xE001 C0004

I2C1STAT - 0xE005 C004

I2DATI2C Data Register. During master or slave transmit mode. data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.R/W0x00

I2C0DAT - 0xE001 C008

I2C1DAT - 0xE005 C008

I2ADRI2C Slave Address Register. Contains the 7 bit slave address for operation of the I2C interface in slave mode. and is not used in master mode. The least significant bit determines whether a slave responds to the general call address.R/W0x00

I2C0ADR - 0xE001 C00C

I2C1ADR - 0xE005 C00C

I2SCLHSCH Duty Cycle Register High Halt Word. Determines the high time of the RC clock.R/W0x04

I2C0SCLH - 0xE001 C010

I2C1SCLH - 0xE005 C010

I2SCLLSCL Duty Cycle Register Low Half Word. Determines the low time of the 12C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.R/W0x04

I2C0SCLL - 0xE001 C014

I2C1SCLL - 0xE005 C014

I2CONCLRI2C Control Clear Register. When a one is written to a bit of this register. the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the PC control register. WONA

I2C0CONCLR - 0xE001 C018

I2C1CONCLR - 0xE005 C018

I2CxCONSET Register

8-bit Register
8 bits Explained

Assert Acknowledge 

AA=1; request an acknowledge


I2C Serial Interrupt

SI=1; indicate state change



STO=1; sends stop condition

STA=1; sends START condition
6I2CENI2CEN=1; I2C interface enable


I2C frequency = [Pclk/(I2CSCLH + I2CSCLL)] .........Hz


  • I2CSCLH: Count for Serial clock High time period
  • I2CSCL : Count for Serial clock low time period

EEPROM interfacing with LPC2148


Algorithm for the Interfacing

1) Start

2) Initialize I2C bus interface

PINSEL0=0X10400050; //Configure P0.11-SCL1 & P0.14-SD1
I2CSCLL=150;   //SET I2C frequency=[Pclk/(I2CSCLL+I2CSCH)]

3) Transmit the slave address(Page address,Page offset,No. of bytes)

4) Enable I2C bus interface


5) Master (LPC2148) will transmit START signal


6) Transmit slave address(7-bit address,R/W=0; write operation)

7) Wait for acknowledgement

8) Tansmit Page address and page offset at which data is to be written

9) Wait for acknowledment

10) Transmit data using I2CDAT register

11) Wait for acknowledge

12) After successful transmission of data , master wil transmit STOP condition


13) Disable I2C interface


14) END 


  • WikiNote Foundation
  • Prof. Sujit Wagh
Created by 1stVolunteer on 2017/06/21 11:38