Data Processing Instructions

Updated on 2017/12/14 21:00

Register Move Operations

  1. MOV r0, r1 ; r0 := r1
    • The MOV instruction loads a value (either a literal or from a source register, e.g. r1) into the destination register (e.g. r0 in this example). A MOV instruction that has the same source and destination registers does not do anything!
  2. MVN r0, r1 ; r0 := not r1
    • MVN is shorthand for "move negated". The MVN instruction take a value (which may be a literal or held in a register), inverts all the bits in this value, and then places it into the destination register.
      • r1: 1101 0110 1010 0000 0111 0101 1010 0011
      • r0: 0010 1001 0101 1111 1000 1010 0101 1100
    • The MVN instruction allows a programmer to put a negative value into a register. As 2's complement is involved, it will be necessary to move one less than the desired value.

Arithmetic Operations

Example: ADD r0, r1, r2 ; r0 := r1 + r2

r1 and r2 are the source registers containing the input operands, r0 is the destination register where the result is stored. The destination register can be the same as one of the source registers, i.e. ADD r0, r0, r1 is legal and means add the values in r0 and r1 together and place the result in r0.

This ADD instruction can be used on both unsigned and 2's complement signed numbers. It may produce a carry out signal and set overflow bits, but such signals are ignored by default.

ADD r0, r1, r2 ; r0 := r1 + r2  (Addition)
ADC r0, r1, r2 ; r0 := r1 + r2 + C (ADD with Carry)
SUB r0, r1, r2 ; r0 := r1 - r2   (Substract)
SBC r0, r1, r2 ; r0 := r1 - r2 + C - 1 (Substract with Carry)
RSB r0, r1, r2 ; r0 := r2 - r1 (Reverse substract)
RSC r0, r1, r2 ; r0 := r2 - r1 + C - 1(Reverse substract with carry)
  • The ADC, SBC, and RSC instructions utilise the value of the carry bit (C) whose value is stored in the Current Program Status Register (covered in the next lecture).
  • Thus the ADC instruction example, ADC r0, r1, r2, adds the values stored in r1 and r2 and the value of the carry bit, placing the result in r0. In the SBC instruction, the carry bit is used to indicate a "borrow", which is unset (set to 0) when a "borrow" is required. These instructions are useful in that they allow programmers to perform arithmetic operations on numbers that are larger than 32 bits.
  • RSB is shorthand for "reverse subtraction" (and RSC is "reverse subtraction with carry") and switches the order of operands for the subtraction process.

Logical Operations

Logical operation are performed bit by bit on the input operands (which may be values in registers or constants) and the result placed in a destination register.

  1. AND r0, r1, r2 ; r0 := r1 (AND)r2 - the result bit is 1 if both input bits are 1
    • r1:  0101 0011  1010 1111    1101 1010   0110 1011
    • r2: 1101  0110  1010 0000 0111 0101   1010 0011
    • r0: 0101 0010 1010 0000 0101 0000 0010 0011
    • AND instructions are useful for "masking" parts of values that you are not interested in currently.
  2. ORR r0, r1, r2 ; r0 := r1 (OR)r2 - the result bit is 1 if either input bit is 1
    • r1: 0101 0011 1010 1111 1101 1010 0110 1011
    • r2: 1101 0110 1010 0000 0111 0101 1010 0011
    • r0: 1101 0111 1010 1111 1111 1111 1110 1011
    • ORR instructions are useful for ensuring that certain bits are set.
  3. EOR r0, r1, r2 ; r0 := r1 (EX-OR) r2 - the result bit is set to 1 if one and only one of
    ;the inputs bits is 1
    • r1: 0101 0011 1010 1111 1101 1010 0110 1011
    • r2: 1101 0110 1010 0000 0111 0101 1010 0011
    • r0: 1000 0101 0000 1111 1010 1111 1100 1000
    • EOR instructions can be useful for inverting specific bits.
  4. BIC r0, r1, r2 ; r0 := r1 (AND)NOT r2
    • BIC stands for 'bit clear', where every '1' in the second operand clears the corresponding bit in the first:
    • r1: 0101 0011 1010 1111 1101 1010 0110 1011
    • r2: 1101 0110 1010 0000 0111 0101 1010 0011
    • r0: 0000 0001 0000 1111 1000 1010 0100 1000
    • BIC instructions can be considered as kind of reverse OR. They can be used to clear specific regions of a word, e.g.
    • r2: 1111 1111 1111 1111 0000 0000 0000 0000
    • would clear the upper halfword leaving the bits in the lower two bytes untouched.

Comparison Operations

There are four comparison operations in ARM assembly language. These comparisons work by performing arithmetic or logical operations on the values stored in the source registers and setting the appropriate condition code flags in the Current Program Status Register as necessary. However, the actual result of the underlying arithmetic or logical operation is not stored in any register.

Note that the comparison operations can have literals instead of registers as operands.

  1. CMP r1,r2; set condition codes according to the result of r1 - r2
    • The CMP (compare) instruction will set the condition codes as follows:
    • N =1 if the most significant bit of (r1 - r2) is 1, i.e. r2 > r1
    • Z = 1 if (r1 - r2) = 0, i.e. r1 = r2
    • C = 1 if r1 and r2 are both unsigned integers AND (r1 < r2)
    • V = 1 if r1 and r2 are both signed integers AND (r1 < r2)
  2. CMN r1, r2    ;set condition codes according to the result of r1 + r2
    • The CMN (compare negative) instruction determines the condition codes by performing the equivalent of: operand1 - ( - operand2). It is useful for comparing the values in registers against small negative numbers (such as -1 which might be used to mark the end of a data structure.)
  3. TST r1, r2    ; set condition codes on r1 AND r2
    • The TST (test bits) instruction can be used to test if one or more bits are set. The first operand is the value to be tested; the second operand is the bit mask. The Z flag will be set if there is a match, otherwise it will be cleared.
  4. TEQ r1, r2    ; set condition codes on r1 XOR r2
    • The TEQ (test equivalent) instruction is similar to TST, but differs in that it uses an exclusive-or operation. It can be used to determine if specific bits in two operands are the same or different. It does not change the overflow flag, unlike CMP. TEQ can be used to determine if two values have the same sign.
  5. ADDS r0, r1, r2    ; r0 := r1 + r2 and update condition flags from CPSR for result placed in r0

NOTE:-The CMP, CMN, TST, and TEQ instructions always alter the condition codes. Other data processing instructions (such as ADD, ADC, SUB, etc.,) can alter the condition codes if they have an "S" suffix.

Multiply instructions

Syntax:
MUL{<cond>} {S} Rd, Rm, Rs
MUL : multiply

  • MUL r0, r1, r2; r0 = r1*r2

MLA : multiply and accumulate

Syntax: MLA{<cond>} {S} Rd, Rm, Rs, Rn

  • MLA r0, r1, r2, r3; r0 = (r1*r2) + r3

Multiply Long Instructions

Syntax: <instruction>{<cond>} {S} RdLo, RdHi, Rm, Rs
Multiply onto a pair of register representing a 64-bit value

UMULL : unsigned multiply long

  • UMULL r0, r1, r2, r3; [r1,r0] = r2*r3

UMLAL : unsigned multiply accumulate long

  • UMLAL r0, r1, r2, r3; [r1,r0] = [r1,r0]+(r2*r3)

SMULL: signed multiply long

  • SMULL r0, r1, r2, r3; [r1,r0] = r2*r3

SMLAL : signed multiply accumulate long

  • SMLAL r0, r1, r2, r3; [r1,r0] = [r1,r0]+(r2*r3)

References

  • WikiNote Foundation
     
Tags:
Created by Vishal E on 2017/04/23 16:28