Control Flow Instruction Set

Updated on 2017/06/20 01:17

Branch Instructions

Basic Branching

This movement around a program is called branching. It is accomplished by suitable branch instructions, sometimes known as jump instructions.

The simplest branch instruction is:

B    label    ; unconditionally branch to the instruction at "label"
      ...          
      ...          
label ...          

The B instruction is an unconditional branch - when the processor encounters such a branch, it always jumps to the designated point. In assembly language, it is possible and desirable to represent the destination of the branch by a symbolic label. The assembler translates this label into the correct memory location, saving the programmer from having to figure out where this actually will be!

Conditional Branches

Conditional branches are much more useful than unconditional branches. If a comparison operation gives a computer the ability to make a decision, conditional branches allow the computer to act on a decision.

In the ARM, conditional branches are executed (taken) or not according to the contents of the four condition codes of the Current Program Status Register (CPSR). For instance, the BNE (branch not equal) instruction refers to the Z bit flag in the CPSR. If the Z bit is set (i.e. some result was zero or a comparison was equal), then the branch is not taken. If the Z bit is clear (i.e. some result was non-zero or a comparison was not equal), then the branch will be taken.

Consider the following example code, which uses a BNE instruction to control a loop:

MOV r0, #5 ; use register r0 as a loop counter and initialize it to the value 5 loop label indicating the start of the loop
...
...
SUB r0, r0, #1 ; decrement the loop counter by subtracting 1 from r0
CMP r0, #0 ; perform a comparison between the value in r0 and zero
BNE loop ; if comparison was not equal, jump back to the loop label and repeat instructions after the end of the loop

Remember that the CMP instruction does not issue a result; rather it tinkers with the condition code bits. The BNE instruction then inspects the Z bit to determine whether the branch should be taken or not. The above code will repeat the loop 5 times before the program can proceed to executing the instructions after the loop's end.

The same program can be rewritten by using the "S" suffix version of the SUB instruction, namely SUBS.

MOV r0, #5 ; use register r0 as a loop counter
                ;and initialize it to the value 5
loop ...       ; label indicating the start of the loop
     ...       ; various instructions that form the body of the loop
     ...       ; and perform useful tasks
SUBS r0, r0, #1; decrement the loop counter by subtracting 1 from r0 and set the condition code bits based on the subtraction result

BNE loop      ; if the Z bit is clear (i.e. "0"), jump back to the loop label and repeat
      ...     ; instructions after the end of the loop

Conditional Branch Instructions

There are 16 possible conditional branches in the ARM assembly language, including "always" (which is effectively an unconditional branch) and "never" (which is never used but exists for future possible extensions to the architecture). The complete set of branch instructions is given in the table:

BranchCondition TestMeaningUses
BNo testUnconditionalAlways take the branch
BALNo testAlwaysAlways take the branch
BEQZ=1EqualComparison equal or zero result
BNEZ=0Not equalComparison not equal or non-zero result
BCSC=1Carry setArithmetic operation gave carry out
BCCC=1Carry clearArithmetic operation did not produce a carry
BHSC=1Higher or sameUnsigned comparison gave higher or same result
BLOC=0LowerUnsigned comparison gave lower result
BMIN=1MinusResult is minus or negative
BPLN=0PlusResult is positive (plus) or zero
BVSV=1Overflow SetSigned integer operation: overflow occurred
BVCV=0Overflow ClearSigned integer operation: no overflow occurred
BHI((NOT C) OR Z) =0
{C set and Z clear}
HigherUnsigned comparison gave higher
BLS((NOT C) OR Z) =1
{C set or Z clear}
Lower or sameUnsigned comparison gave lower or same
BGE(N EOR V) =0
{(N and V) set or (N and V) clear}
Greater or EqualSigned integer comparison gave greater than or equal
BLT(N EOR V) =1
{(N set and V clear) or (N clear and V set)}
Less ThanSigned integer comparison gave less than
BGT(Z OR (N EOR V)) =0
{((N and V) set or clear) and Z clear}
Greater ThanSigned integer comparison gave greater than
BLE(Z OR (N EOR V)) =1
{(N set and V clear) or (N clear and V set) or Z set}
Less or EqualSigned integer comparison gave less than or equal

Conditional Execution

  • Unlike most processor architectures, all instructions in the ARM assembly language can be conditionally executed.
  • The ADDNE and SUBNE instructions are executed only if the Z bit is "0", i.e. the CMP instruction had a non-zero result and cleared the Z bit.
  • This form of conditional execution is efficient if the conditional sequence is only three or less instructions. For longer sequences, it is more efficient to use proper loops and conventional branching.
  • The "S" suffix can be appended to instructions with the conditional suffices, enabling them to adjust the condition codes. However this can lead to unexpected behaviour in succeeding instructions.

Let r0 be 4, r1 be -4, and r2 be 7. Alter the code from above to be as follows:

CMP r0,#10 ; compare the value in r0 with the value 10
ADDNE r1, r1, r0; r0 ≠10, so Z is 0, so r1 = -4 + 4, and Z is now set
SUBNE r2, r2, r0; Z is set (i.e. "1"), so SUBNE is not executed
...         ; other code now follows

The conditional suffix mnemonics are the same as for conditional branches:

SuffixCondition TestMeaning
EQZ=1Equal
NEZ=0Not Equal
CSC=1Carry Set (Unsigned Higher or Same)
CCC=1Carry Clear (Unsigned Lower than)
MIN=1Minus
PLN=0Plus
VSV=1Overflow Set
VCV=0Overflow Clear
HI((NOT C) OR Z) =0
{C set and Z clear}
Higher unsigned
LS((NOT C) OR Z) =1
{C set or Z clear}
Lower or same unsigned
GE(N EOR V) =0
{(N and V) set or (N and V) clear}
Greater or Equal
LT(N EOR V) =1
{(N set and V clear) or (N clear and V set)}
Less Than
GT(Z OR (N EOR V)) =0
{((N and V) set or clear) and Z clear}
Greater Than
LE(Z OR (N EOR V)) =1
{(N set and V clear) or (N clear and V set) or Z set}
Less or Equal

References

  • WikiNote Foundation
  • www-mdp.eng.cam.ac.uk
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Created by Vishal E on 2017/04/23 16:30