ARM7 Data Flow Model, Programmer's Model

Updated on 2017/06/21 11:56

Syllabus

ARM7 Fundamentals, Data Flow Model, Programmer's Model

ARM7 Fundamentals

  1. All ARM instructions are 32-bit long & stored word aligned.
  2. ARM processor like all RISC processors is a Load Store architecture, Von-Neuman Architecture (same program + data memory).
  3. ARM has two special instructions types for transferring data in & data out of processor.
    • Load Instruction = Copy data from memory to registers in the core.
      • (Registers in the processor core <----Memory)
    • Store Instruction = Copy data from registers to memory
      • (Registers in processor core ----> Memory)
  4. There are no data processing instructions that are directly manipulate data in memory (Hence Data processing is carried out only in registers).
  5. ARM core is a 32-bit bit processor most instructions treat the registers ad holding signed or unsigned 32-bit value.
  6. Data Types
  7. Word – 32-bit, Halfword – 16-bit, Byte – 8-bit
    • Memory is byte addressable, can hold 232 bytes (= 4 GB)  
    • Word/ halfword /byte size data are placed at word/ halfword/ byte aligned addresses.
    • 32-bit ARM instructions are placed at word aligned addresse.
  8. Byte order – Endian format
    • Word/halfword size data can be saved/retrieved in big endian or little endian format.
    • Big endian: MSB of word/halfword data are stored in lowest address and the data is addressed by address of MSB
    • Little endian: LSB of word/halfword data are stored in lowest address and the data is addressed by address of LSB

Advanced Microcontroller Bus Architecture (AMBA)

ARM_BUS.png

  • Bus system connects memory, controllers and peripherals in ARM processor based microcontroller to ARM core
  • AMBA bus protocol std., adopted as on-chip bus by many mC 
  • ARM core is bus master, peripherals are slaves

Three Buses within AMBA spec

  1. AHP (Advanced High-performance Bus)

    • Provides high band-width. 
    • Supports multiple masters, slaves (e.g. of masters: DMA, Test interface, DSP, and e.g. of slaves: external memory).
    • Includes bus arbiter, decoder
    • Used in complex and more sophisticated systems
  2. ASB (Advanced System Bus)

    • AHB and ASB have many things in common
    • Both support bursting, pipelining, split transaction
    • ASB is used in simple cost effective designs
  3. APB (Advanced Peripheral Bus)

    • Simple, low speed, low power bus, for UART, .... peripherals
    • Implemented with simple tri-stated data bus
    • AHB-APB bridge: buffers data & operations between the two

ARM Core Data Flow Model

Definition

When an instruction is decoded inside the ARM core and how a particular instruction is executed by interacting with the internal registers file and then send result out of the registers.

ARM Data flow model.jpg       

Features

  • Von Neuman Architecture Hence data coming through bus is either instruction or data (same memory).
  • The Sign extend hardware converts signed 8-bit & 16-bit numbers to 32-bit values as they are read from memory & placed in a register (for signed values), fill zeros if unsigned.
  • Source operands (Rn & Rm) are read from the register file using the internal buses A & B respectively & result Rd is written back.
  • The PC value is in the address register which is fed in to the incrementer, then the incremented value is copied back in to r15.
  • It is also written in to address register to be used as the address for the next instruction fetch.
  • ALU: (The Arithmetic & logic Unit) or MAC (multiply & accumulate Unit) takes the register values Rn & Rm from A & B buses & computers a result).
  • Data processing instructions write the result in Rd directly to the register file.
  • Load & Store instruction use the ALU to generate on Address  to be to be held in the address register & broadcast on the address bus.
  • Barrel shifter:
    • One important feature of the is that register Rm alternatively can be pre processed in barrel in barrel shifter before it enters the ALU [left shift , right shift , rotated etc.].
    • Depending on the instruction Barrel Shifter may be used or it could be short circuit.
    • Barrel shifter & ALU can calculate together a wide range of expression & address in the same cycle.

ARM7 Processor Modes

Definition: It determines which register are active  & The access to the CPSR register itself.

Privileged 
(Allows full read-write access to CPSR)

Non- privileged

(Only allows read access to the control field in CPSR but allows read-write  access to conditional flags)

  • Fast interrupt request            
  • Interrupt request
  • System
  • Supervisor
  • Undefined
  • Abort
  • User mode

Mode

When does ARM enters in pericular mode?

Abort

Failed attempt to access memory.

Fast interrupt request

Interrupt request arrives through FIQ channel (input).

Interrupt request

Interrupt request arrives through IRQ channel (output).

Supervisor

After reset. It is generally the mode that an OS Kernel operates in.

System

Special version of user mode that allows full read-write access to the CPSR.

Undefined

When processor encounters an instruction. That is undefined or not supported by the implementation.

User mode

Used for programs & applications

ARM7 Programmer's Model or Register Model

Diagram

Programmers model.jpg

Explained

  • In total 17(Visible)+20(Banked Rrgisters)=37 
  • The active registers available in the user mode are shown below.
  • This is protected mode which is normally used while executing applications.
  • 16 Data registers & one status register 
  • r0 to  r13 are orthogonal general purpose register.
  • Orthogonal means, any instruction that you can apply to ro can equally be applied to any of the other register.
    • Eg. ADD ro, r1, r2
    • ADD r5, r6, r7
  • R13 (stack pointer) and stores the top of the stack in the current processor mode.
  • R14(LR) Link Register where the core puts the return address on executing a subroutine.
  • R15(PC) Program counter stores the address of next instruction to be executed.
  • In ARM state all ARM instruction  are 32-bits wide.
  • In Thumb state all instructions are 16-bit wide.
  • In ARM state Instruction have to be four byte aligned in the memory. Which implies that the bottom two bits of the PC are always zero(Memory location 1000H,1004,1008H).

CPSR: Current Processor Status Register

About CPSR

  • ARM core uses CPSR to moniter & control internal operations.
  • The unused part reserved for future expansion.
  • CPSR fields is divided in to four fields, each 8-bits wide: flags, status, extension, and control.
  • In current designs status & extension fields are reserved for for future purpose.
  • In some ARM processor cores have extra bits allocated J bit (available only on Jazelle enabled processing which execute 8-bit instructions).

CPSR Diagram

cpsr.jpg

Flag bitSets when

N- Negative         

In case of signed no. operations If result 

MSB=1  ;Indicates the result of operation is NEGATIVE

Z- Zero    The result of operation is zero
C- CarryThe result causes an unsigned carry(carry out of MSB)
V-OverflowThe result causes a signed overflow
Q- SaturationThe result causes an overflow or saturation
I- Interrupt request DisableIf set interrupt request channel is disabled
F- Fast interrupt request Disable If set fast interrupt request channel is disabled
J- Jazelle instruction setIf set processor will execute Jazelle instructions
T-Thumb instruction set  If set processor will execute Thumb Instruction set

SPSR: Save Program Status Register

Suppose Processor is in USER mode of operation and if IRQ request arrives then processor has to switch itself to IRQ mode of operation but at the same after serving IRQ mode processor should return to USER mode and should resume its working.
So current processor status is copied into SPSR from CPSR in order to resume back.

Exceptions

  • Generated by external events or internal sources
  • Seven types of exceptions
    1. Reset: Occurs when ‘Reset’ pin is asserted – power-up/reset
    2. Undefined: Occurs when currently executing instruction could not be recognized
    3. SWI: Occurs if program in user mode executes  SWI instruction to request OS services that are available in supervisor mode.
    4. Prefetch Abort: Occurs if instruction fetched from invalid address. Exception is generated at execution stage.
    5. Data Abort: Occurs if data load/store attempt at illegal address
    6. IRQ: Occurs if IRQ pin goes low (only if CPSR IRQ mask bit is 0)
    7. FIQ: Occurs if FIQ pin goes low (only if CPSR FIQ mask bit is 0)

References

  • ARM website
  • ARM System Developers Guide by Andrew Sloss
  • ARM Processors by Dr. Mathivanan
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Created by 1stVolunteer on 2017/06/21 11:53