Unit 1: Combinational Logic Design

Updated on 2017/08/19 10:27

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Unit 1: Combinational Logic Design

  • Standard representations for logic functions, k map representation of logic functions (SOP and POS forms), minimization of logical functions for min-terms and max-terms (upto 4 variables), don’t care conditions, Design Examples: Arithmetic Circuits, BCD - to – 7 segment decoder, Code converters. Adders and their use as subtractor, look ahead carry, ALU, Digital Comparator, Parity generators/checkers, Multiplexers and their use in combinational logic designs, multiplexer trees, De-multiplexers and their use in combinational logic designs, Decoders, demultiplexer trees. Introduction to QuineMcCluskey method.  

References

  • WikiNote Foundation
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Created by Sujit Wagh on 2017/08/19 10:27